GC5318 Datasheet, PDF (11/45 Pages) Texas Instruments – HIGH-DENSITY DIGITAL UPCONVERTER

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GC5318
HIGH-DENSITY DIGITAL UPCONVERTER
SLWS187 – JULY 2006
Each transmit channel includes an RMS power meter used to measure the RMS power within the channel.
The RMS power meter samples the I and Q data stream before the PFIR filter; see Figure 2-7. Both 18-bit
I and Q data are squared, summed, and then integrated over a time determined by
pmeter_integration_duc (13 bits). The integration time = 4 x pmeter_integration_duc + 1 (in units of a
sample period or generally a chip period).
A programmable 9-bit interval counter sets the interval over which power measurements are repeated.
The timer counts in increments of 64 samples. The interval time = 64 (pmeter_interval_duc+1). The
interval time must be greater than (not equal to) the integration time.
The power measurement process starts with a sync event (ssel_pmeter). The integration starts at sync
event + 3 chips + sync_delay. The 7-bit delay register permits delays from three to 130 samples after
sync. The integration continues until the integration count is met. At that point, the top 32 bits of the 50-bit
accumulator are transferred to the read register and an interrupt is generated that indicates the power
value is ready to read. The interval counter continues until the programmed interval count is reached.
When reached, the integration counter and the interval counter start over again. Each time the integration
count is reached the upper 32 bits are again transferred to the read register, overwriting the previous
value and sending an interrupt signifying the power value can be read. Failure to read the data before the
next interrupt signal results in overwriting the previous interval measurement.
Sync ssel_pmeter starts the process. Whenever a sync is received, all counters are reset to zero no
matter what the status may be.
For UMTS, I and Q are calculated and the integrated power is read. In CDMA mode the power is
calculated for both the A and B signals, producing two 32-bit results.
For CDMA mode, the integration time is slightly longer. The power read in CDMA mode with a dc input is:
• A power: [ I² × (X × 4 + 1) + Q² × (X × 4 + 0) ] × 2^-18. Note: One Q sample is missing from the
integration.
• B power: [ I² × (X × 4 + 1) + Q² × (X × 4 + 1) ] × 2^-18
where X is the integration count.
Table 2-5. Programming
VARIABLE
pmeter_result_a_lsb(15:0)
pmeter_result_a_msb (31:16)
pmeter_result_b_lsb (15:0)
pmeter_integration_duc(12:0)
pmeter_sync_delay_duc(6:0)
pmeter_interval_duc(9:0)
ssel_pmeter(2:0)
pmeter_sync_disable
DESCRIPTION
Lower 16 bits of the A channel power measurement.
Upper 16 bits of the A channel power measurement.
Lower 16 bits of the B channel power measurement result. Only available in CDMA mode.
Integration time = 4 x pmeter_integration_duc + 1.
Sync delay count in samples.
Interval time = 64 (pmeter_interval_duc + 1). Interval time must be greater than (not equal to) integration
time.
Sync source options.
Turns off sync to the channel's power meter
GC5318 Operation
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