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CC2500 Datasheet, PDF (67/76 Pages) Texas Instruments – Single Chip Low Cost Low Power RF Transceiver
Bit Field Name
7:0 EVENT0[7:0]
Bit Field Name
7 RC_PD
6:4 EVENT1[2:0]
3 RC_CAL
2 Reserved
1:0 WOR_RES
Bit Field Name
7:0 FREND1[7:0]
CC2500
0x1F: WOREVT0 – Low byte Event0 timeout
Reset
R/W Description
107 (0x6B) R/W
Low byte of Event 0 timeout register.
The default Event 0 value gives 1.0s timeout, assuming a
26.0 MHz crystal.
0x20: WORCTRL – Wake On Radio control
Reset R/W Description
1
7 (111)
1
0 (00)
R/W Power down signal to RC oscillator. When written to 0, automatic
initial calibration will be performed
R/W Timeout setting from register block. Decoded to Event 1 timeout.
RC oscillator clock frequency equals FXOSC/750, which is 34.7-36
kHz, depending on crystal frequency. The table below lists the
number of clock periods after Event 0 before Event 1 times out.
Setting WOR_AUTOSYNC=0
WOR_AUTOSYNC=1
0 (000) 4 (0.111 – 0.115 ms)
16 (0.44 – 0.46 ms)
1 (001) 6 (0.167 – 0.173 ms)
24 (0.67 – 0.69 ms)
2 (010) 8 (0.222 – 0.230 ms)
32 (0.89 – 0.92 ms)
3 (011) 12 (0.333 – 0.346 ms)
48 (1.33 – 1.38 ms)
4 (100) 16 (0.444 – 0.462 ms)
64 (1.78 – 1.85 ms)
5 (101) 24 (0.667 – 0.692 ms)
96 (2.67 – 2.77 ms)
6 (110) 32 (0.889 – 0.923 ms)
128 (3.56 – 3.69 ms)
7 (111) 48 (1.333 – 1.385 ms)
192 (5.33 – 5.54 ms)
R/W Enables (1) or disables (0) the RC oscillator calibration.
Included for debug/test purposes only.
R0
R/W Controls the Event 0 resolution and maximum timeout of the WOR
module:
Setting Resolution (1 LSB)
Max timeout
0 (00)
1 (01)
2 (10)
3 (11)
1 period (28 – 29 µs)
25 periods (0.89 – 0.92 ms)
210 periods (28 – 30 ms)
215 periods (0.91 – 0.94 s)
1.8 – 1.9 seconds
58 – 61 seconds
31 – 32 minutes
16.5 – 17.2 hours
Adjusting the resolution does not affect the resolution of the WOR
time readout registers WORTIME1/WORTIME0.
0x21: FREND1 – Front end RX configuration
Reset R/W Description
166
R/W Front end RX configuration. The value to use in this register
(0xA6)
is given by the SmartRF® Studio software.
Preliminary Data Sheet (rev.1.1.) SWRS040
Page 67 of 77