CC2500 Datasheet, PDF (38/76 Pages) Texas Instruments – Single Chip Low Cost Low Power RF Transceiver

CC2500
20 Data FIFO
The CC2500 contains two 64 byte FIFOs, one
for received data and one for data to be
transmitted. The SPI interface is used to read
from the RX FIFO and write to the TX FIFO.
Section 10.4 contains details on the SPI FIFO
access. The FIFO controller will detect
overflow in the RX FIFO and underflow in the
TX FIFO.
When writing to the TX FIFO it is the
responsibility of the MCU to avoid TX FIFO
overflow. A TX FIFO overflow will result in an
error in the TX FIFO content.
Likewise, when reading the RX FIFO the MCU
must avoid reading the RX FIFO past its
empty value, since an RX FIFO underflow will
result in an error in the data read out of the RX
FIFO.
The chip status byte that is available on the SO
pin while transferring the SPI address contains
the fill grade of the RX FIFO if the address is a
read operation and the fill grade of the TX
FIFO is the address is a write operation.
Section 10.1 on page 20 contains more details
on this.
The number of bytes in the RX FIFO and TX
FIFO can also be read from the status
registers RXBYTES.NUM_RXBYTES and
TXBYTES.NUM_TXBYTES respectively. If
receiving data while reading the last byte in
the RX FIFO, the RX FIFO pointer is not
updated, resulting in a duplication of the last
byte read.
To avoid this problem one should never empty
the RX FIFO before the last byte of the packet
is received. The following software fix can be
used:
1. Read RXBYTES.NUM_RXBYTES
2. If RXBYTES.NUM_RXBYTES < packet
length, read RXBYTES.NUM_RXBYTES-1
bytes from the FIFO
3. Repeat until RXBYTES.NUM_RXBYTES =
number of remaining bytes of the packet
4. Read the remaining bytes from the FIFO
The 4-bit FIFOTHR.FIFO_THR setting is used
to program threshold points in the FIFOs.
Table 29 lists the 16 FIFO_THR settings and
the corresponding thresholds for the RX and
TX FIFOs. The threshold value is coded in
opposite directions for the RX FIFO and TX
FIFO. This gives equal margin to the overflow
and underflow conditions when the threshold
is reached.
A flag will assert when the number of bytes in
the FIFO is equal to or higher than the
programmed threshold. The flag is used to
generate the FIFO status signals that can be
viewed on the GDO pins (see Section 28 on
page 45).
Figure 15 shows the number of bytes in both
the RX FIFO and TX FIFO when the threshold
flag toggles, in the case of FIFO_THR=13.
Figure 14 shows the flag as the respective
FIFO is filled above the threshold, and then
drained below.
NUM_RXBYTES 53 54 55 56 57 56 55 54 53
GDO
NUM_TXBYTES 6 7 8 9 10 9 8 7 6
GDO
Figure 14: FIFO_THR=13 vs. number of bytes
in FIFO (GDOx_CFG=0x00 in Rx and
GDOx_CFG=0x02 in Tx)
FIFO_THR
0 (0000)
1 (0001)
2 (0010)
3 (0011)
4 (0100)
5 (0101)
6 (0110)
7 (0111)
8 (1000)
9 (1001)
10 (1010)
11 (1011)
12 (1100)
13 (1101)
14 (1110)
15 (1111)
Bytes in TX FIFO
61
57
53
49
45
41
37
33
29
25
21
17
13
9
5
1
Bytes in RX FIFO
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
64
Table 29: FIFO_THR settings and the
corresponding FIFO thresholds
Preliminary Data Sheet (rev.1.1.) SWRS040
Page 38 of 77