CC2500 Datasheet, PDF (40/76 Pages) Texas Instruments – Single Chip Low Cost Low Power RF Transceiver

CC2500
22 VCO
The VCO is completely integrated on-chip.
22.1 VCO and PLL Self-Calibration
The VCO characteristics will vary with
temperature and supply voltage changes, as
well as the desired operating frequency. In
order to ensure reliable operation, CC2500
includes frequency synthesizer self-calibration
circuitry. This calibration should be done
regularly, and must be performed after turning
on power and before using a new frequency
(or channel). The number of XOSC cycles for
completing the PLL calibration is given in
Table 28 on page 37.
The calibration can be initiated automatically
or manually. The synthesizer can be
automatically calibrated each time the
synthesizer is turned on, or each time the
synthesizer is turned off. This is configured
with the MCSM0.FS_AUTOCAL register setting.
In manual mode, the calibration is initiated
when the SCAL command strobe is activated
in the IDLE mode.
Note that the calibration values are maintained
in sleep mode, so the calibration is still valid
after waking up from sleep mode (unless
supply voltage or temperature has changed
significantly).
23 Voltage Regulators
CC2500 contains several on-chip linear voltage
regulators, which generate the supply voltage
needed by low-voltage modules. These
voltage regulators are invisible to the user, and
can be viewed as integral parts of the various
modules. The user must however make sure
that the absolute maximum ratings and
required pin voltages in Table 1 and Table 13
are not exceeded. The voltage regulator for
the digital core requires one external
decoupling capacitor.
Setting the CSn pin low turns on the voltage
regulator to the digital core and starts the
crystal oscillator. The SO pin on the SPI
interface must go low before using the serial
interface (setup time is given in Table 16).
If the chip is programmed to enter power-down
mode, (SPWD strobe issued), the power will be
turned off after CSn goes high. The power and
crystal oscillator will be turned on again when
CSn goes low.
The voltage regulator output should only be
used for driving the CC2500.
24 Output Power Programming
The RF output power level from the device has
two levels of programmability, as illustrated in
Figure 16. Firstly, the special PATABLE
register can hold up to eight user selected
output power settings. Secondly, the 3-bit
FREND0.PA_POWER value selects the
PATABLE entry to use. This two-level
functionality provides flexible PA power ramp
up and ramp down at the start and end of
transmission. All the PA power settings in the
PATABLE from index 0 up to the
FREND0.PA_POWER value are used.
The power ramping at the start and at the end
of a packet can be turned off by setting
FREND0.PA_POWER to zero and then
program the desired output power to index
zero in the PATABLE.
Table 31 contains recommended PATABLE
settings for various output levels and
frequency bands. See Section 10.5 on page
22 for PATABLE programming details.
PATABLE must be programmed in burst mode
if you want to write to other entries than
PATABLE[0].
Preliminary Data Sheet (rev.1.1.) SWRS040
Page 40 of 77