CC2500 Datasheet, PDF (20/76 Pages) Texas Instruments – Single Chip Low Cost Low Power RF Transceiver

CC2500
t _sp
t _ch
t _cl
t_sd
t_hd
t _ns
SCLK:
CSn:
Write to register:
SI ^X
0
A6 A5 A4 A3 A2 A1 A0 X D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
W
W
W
W
W
W
W
W
X
SO ^{Hi-Z S7}
S6
S5
S4
S3
S2
S1
S0
S7
S6 S5 S4 S3 S2 S1 S0 S7 Hi-Z
Read from register:
SI ^X
1
A6 A5
A4 A3 A2 A1 A0
X
SO ^{Hi-Z S7}
S6
S5
S4
S3
S2
S1
S0
D7
D6 D 5 D4 D3 D 2 D1
R
R
R
R
R
R
R
D0
R
Hi-Z
Figure 6: Configuration registers write and read operations (A6 is the “burst” bit)
Parameter
F_SCLK
t_sp,pd
t_sp
t_ch
t_cl
t_rise
t_fall
t_sd
t_hd
t_ns
Description
Min
SCLK frequency
0
CSn low to positive edge on SCLK, in power-down mode
TBD
CSn low to positive edge on SCLK, in active mode
TBD
Clock high
50
Clock low
50
Clock rise time
-
Clock rise time
-
Setup data to positive edge on SCLK
TBD
Hold data after positive edge on SCLK
TBD
Negative edge on SCLK to CSn high.
TBD
Table 16: SPI interface timing requirements
Max
10
-
-
-
-
TBD
TBD
-
-
-
Units
MHz
µs
ns
ns
ns
ns
ns
ns
ns
ns
CSn:
Command strobe(s):
Read or write register(s):
Read or write consecutive registers (burst):
Read or write n+1 bytes from/to RF FIFO:
Combinations:
ADDR_strobe ADDR_strobe ADDR_strobe ...
ADDR_reg DATA ADDR_reg DATA ADDR_reg DATA ...
ADDR_{reg n} DATA_n DATA_n+1 DATA_n+2
...
ADDR_FIFO DATA_{byte 0} DATA_{byte 1} DATA_{byte 2}
...
DATA_{byte n-1} DATA_{byte n}
ADDR_reg DATA ADDR_strobe ADDR_reg DATA ADDR_strobe ADDR_FIFO DATA_{byte 0} DATA_{byte 1} ...
Figure 7: Register access types
10.1 Chip Status Byte
When the header byte, data byte or command
strobe is sent on the SPI interface, the chip
status byte is sent by the CC2500 on the SO
pin. The status byte contains key status
signals, useful for the MCU. The first bit, s7, is
the CHIP_RDYn signal; this signal must go low
before the first positive edge of SCLK. The
CHIP_RDYn signal indicates that the crystal is
running and the regulated digital supply
voltage is stable.
Preliminary Data Sheet (rev.1.1.) SWRS040
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