CC2500 Datasheet, PDF (22/76 Pages) Texas Instruments – Single Chip Low Cost Low Power RF Transceiver

CC2500
10.3 Command Strobes
Command Strobes may be viewed as single
byte instructions to CC2500. By addressing a
Command Strobe register, internal sequences
will be started. These commands are used to
disable the crystal oscillator, enable receive
mode, enable wake-on-radio etc. The 14
command strobes are listed in Table 34 on
page 50.
The command strobe registers are accessed
in the same way as for a register write
operation, but no data is transferred. That is,
only the R/W bit (set to 0), burst access (set to
0) and the six address bits (in the range 0x30
through 0x3D) are written. A command strobe
may be followed by any other SPI access
without pulling CSn high. The command
strobes are executed immediately, with the
exception of the SPWD and the SXOFF strobes
that are executed when CSn goes high.
When writing command strobes, the status
byte is sent on the SO pin.
10.4 FIFO Access
The 64-byte TX FIFO and the 64-byte RX
FIFO are accessed through the 0x3F address.
When the read/write bit is zero, the TX FIFO is
accessed, and the RX FIFO is accessed when
the read/write bit is one.
The TX FIFO is write-only, while the RX FIFO
is read-only.
The burst bit is used to determine if FIFO
access is single byte or a burst access. The
single byte access method expects address
with burst bit set to zero and one data byte.
After the data byte a new address is expected;
hence, CSn can remain low. The burst access
method expects one address byte and then
consecutive data bytes until terminating the
access by setting CSn high.
The following header bytes access the FIFOs:
• 0x3F: Single byte access to TX FIFO
• 0x7F: Burst access to TX FIFO
• 0xBF: Single byte access to RX FIFO
• 0xFF: Burst access to RX FIFO
When writing to the TX FIFO, the status byte
(see Section 10.1) is output for each new data
byte on SO, as shown in Figure 6. This status
byte can be used to detect TX FIFO underflow
while writing data to the TX FIFO. Note that
the status byte contains the number of bytes
free before writing the byte in progress to the
TX FIFO. When the last byte that fits in the TX
FIFO is transmitted to the SI pin, the status
byte received concurrently on the SO pin will
indicate that one byte is free in the TX FIFO.
The transmit FIFO may be flushed by issuing a
SFTX command strobe. Similarly, a SFRX
command strobe will flush the receive FIFO. A
SFTX or SFRX command strobe can only be
issued in the IDLE, TXFIFO_UNDERLOW or
RXFIFO_OVERFLOW state. Both FIFOs are
flushed when going to the SLEEP state.
10.5 PATABLE Access
The 0x3E address is used to access the
PATABLE, which is used for selecting PA
power control settings. The SPI expects up to
eight data bytes after receiving the address.
By programming the PATABLE, controlled PA
power ramp-up and ramp-down can be
achieved. See Section 0 on page 40 for output
power programming details.
The PATABLE is an 8-byte table that defines
the PA control settings to use for each of the
eight PA power values (selected by the 3-bit
value FREND0.PA_POWER). The table is
written and read from the lowest setting (0) to
the highest (7), one byte at a time. An index
counter is used to control the access to the
table. This counter is incremented each time a
byte is read or written to the table, and set to
the lowest index when CSn is high. When the
highest value is reached the counter restarts
at zero.
The access to the PATABLE is either single
byte or burst access depending on the burst
bit. When using burst access the index counter
will count up; when reaching 7 the counter will
restart at 0. The read/write bit controls whether
the access is a write access (R/W=0) or a read
access (R/W=1).
If one byte is written to the PATABLE and this
value is to be read out then CSn must be set
high before the read access in order to set the
index counter back to zero.
Note that the content of the PATABLE is lost
when entering the SLEEP state, except for the
first byte (index 0).
Preliminary Data Sheet (rev.1.1.) SWRS040
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