CC2500 Datasheet, PDF (21/76 Pages) Texas Instruments – Single Chip Low Cost Low Power RF Transceiver

CC2500
Bits 6, 5 and 4 comprise the STATE value.
This value reflects the state of the chip. The
XOSC and power to the digital core is on in
the IDLE state, but all other modules are in
power down. The frequency and channel
configuration should only be updated when the
chip is in this state. The RX state will be active
when the chip is in receive mode. Likewise, TX
is active when the chip is transmitting.
The last four bits (3:0) in the status byte con-
tains FIFO_BYTES_AVAILABLE. For read
operations, the FIFO_BYTES_AVAILABLE
field contains the number of bytes available for
reading from the RX FIFO. For write
operations, the FIFO_BYTES_AVAILABLE
field contains the number of bytes free for
writing into the TX FIFO. When
FIFO_BYTES_AVAILABLE=15, 15 or more
bytes are available/free.
Table 17 gives a status byte summary.
Bits Name
Description
7 CHIP_RDYn
Stays high until power and crystal have stabilized. Should always be low when using
the SPI interface.
6:4 STATE[2:0]
Indicates the current main state machine mode
Value State
Description
000 IDLE
Idle state
(Also reported for some transitional states instead
of SETTLING or CALIBRATE)
001 RX
Receive mode
010 TX
Transmit mode
011 FSTXON
Frequency synthesizer is on, ready to start
transmitting
100 CALIBRATE
Frequency synthesizer calibration is running
101 SETTLING
PLL is settling
110 RXFIFO_OVERFLOW RX FIFO has overflowed. Read out any
useful data, then flush the FIFO with SFRX
111 TXFIFO_UNDERFLOW TX FIFO has underflowed. Acknowledge with
SFTX
3:0 FIFO_BYTES_AVAILABLE[3:0] The number of bytes available in the RX FIFO or free bytes in the TX FIFO
(depends on the read/write-bit). If FIFO_BYTES_AVAILABLE=15, there are 15 or
more bytes in RX FIFO or 49 or less bytes in the TX FIFO.
Table 17: Status byte summary
10.2 Register Access
The configuration registers of the CC2500 are
located on SPI addresses from 0x00 to 0x2F.
Table 35 on page 51 lists all configuration
registers. The detailed description of each
register is found in Section 31.1, starting on
page 54. All configuration registers can be
both written to and read. The read/write bit
controls if the register should be written to or
read. When writing to registers, the status byte
is sent on the SO pin each time a header byte
or data byte is transmitted on the SI pin.
When reading from registers, the status byte is
sent on the SO pin each time a header byte is
transmitted on the SI pin.
Registers with consecutive addresses can be
accessed in an efficient way by setting the
burst bit in the address header. The address
sets the start address in an internal address
counter. This counter is incremented by one
each new byte (every 8 clock pulses). The
burst access is either a read or a write access
and must be terminated by setting CSn high.
For register addresses in the range 0x30-
0x3D, the “burst” bit is used to select between
status registers and command strobes (see
below). The status registers can only be read.
Burst read is not available for status registers,
so they must be read one at a time.
Preliminary Data Sheet (rev.1.1.) SWRS040
Page 21 of 77