OMAP-L138_10 Datasheet, PDF (66/268 Pages) Texas Instruments – Low-Power Applications Processor

OMAP-L138 Low-Power Applications Processor
SPRS586A – JUNE 2009 – REVISED AUGUST 2009
www.ti.com
this function.
• Control of on-chip inter-processor interrupts for signaling between ARM and DSP
Since the SYSCFG peripheral controls global operation of the device, its registers are protected against
erroneous accesses by several mechanisms:
• A special key sequence must be written to KICK0, KICK1 registers before any other registers are
writeable.
• Additionally, many registers are accessible only by a host (ARM or DSP) when it is operating in its
privileged mode. (ex. from the kernel, but not from user space code).
Register Address
0x01C1 4000
0x01C14008
0x01C1400C
0x01C14010
0x01C14014
0x01C1 4020
0x01C1 4038
0x01C1 403C
0x01C1 4040
0x01C1 4044
0x01C1 40E0
0x01C1 40E4
0x01C1 40E8
0x01C1 40EC
0x01C1 40F0
0x01C1 40F4
0x01C1 40F8
0x01C1 4110
0x01C1 4114
0x01C1 4118
0x01C1 4120
0x01C1 4124
0x01C1 4128
0x01C1 412C
0x01C1 4130
0x01C1 4134
0x01C1 4138
0x01C1 413C
0x01C1 4140
0x01C1 4144
0x01C1 4148
0x01C1 414C
0x01C1 4150
0x01C1 4154
0x01C1 4158
0x01C1 415C
0x01C1 4160
0x01C1 4164
Table 4-1. System Configuration (SYSCFG) Module Register Access
Register Name
REVID
DIEIDR0
DIEIDR1
DIEIDR2
DIEIDR3
BOOTCFG
KICK0R
KICK1R
HOST0CFG
HOST1CFG
IRAWSTAT
IENSTAT
IENSET
IENCLR
EOI
FLTADDRR
FLTSTAT
MSTPRI0
MSTPRI1
MSTPRI2
PINMUX0
PINMUX1
PINMUX2
PINMUX3
PINMUX4
PINMUX5
PINMUX6
PINMUX7
PINMUX8
PINMUX9
PINMUX10
PINMUX11
PINMUX12
PINMUX13
PINMUX14
PINMUX15
PINMUX16
PINMUX17
Register Description
Revision Identification Register
Device Identification Register 0
Device Identification Register 1
Device Identification Register 2
Device Identification Register 3
Boot Configuration Register
Kick 0 Register
Kick 1 Register
Host 0 Configuration Register
Host 1 Configuration Register
Interrupt Raw Status/Set Register
Interrupt Enable Status/Clear Register
Interrupt Enable Register
Interrupt Enable Clear Register
End of Interrupt Register
Fault Address Register
Fault Status Register
Master Priority 0 Registers
Master Priority 1 Registers
Master Priority 2 Registers
Pin Multiplexing Control 0 Register
Pin Multiplexing Control 1 Register
Pin Multiplexing Control 2 Register
Pin Multiplexing Control 3 Register
Pin Multiplexing Control 4 Register
Pin Multiplexing Control 5 Register
Pin Multiplexing Control 6 Register
Pin Multiplexing Control 7 Register
Pin Multiplexing Control 8 Register
Pin Multiplexing Control 9 Register
Pin Multiplexing Control 10 Register
Pin Multiplexing Control 11 Register
Pin Multiplexing Control 12 Register
Pin Multiplexing Control 13 Register
Pin Multiplexing Control 14 Register
Pin Multiplexing Control 15 Register
Pin Multiplexing Control 16 Register
Pin Multiplexing Control 17 Register
Register Access
—
—
—
—
—
Privileged mode
Privileged mode
Privileged mode
—
—
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
—
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
66
Device Configuration
Submit Documentation Feedback