OMAP-L138_10 Datasheet, PDF (129/268 Pages) Texas Instruments – Low-Power Applications Processor

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OMAP-L138 Low-Power Applications Processor
SPRS586A – JUNE 2009 – REVISED AUGUST 2009
6.13 Serial ATA Controller (SATA)
The Serial ATA Controller (SATA) provides a single HBA port operating in AHCI mode and is used to
interface to data storage devices at both 1.5 Gbits/second and 3.0 Gbits/second line speeds. AHCI
describes a system memory structure that contains a generic area for control and status, and a table of
entries describing a command list where each command list entry contains information necessary to
program an SATA device, and a pointer to a descriptor table for transferring data between system memory
and the device.
The SATA Controller supports the following features:
• Serial ATA 1.5 Gbps (Gen 1i) and 3 Gbps (Gen 2i) line speeds
• Support for the AHCI controller spec 1.1
• Integrated SERDES PHY
• Integrated Rx and Tx data buffers
• Supports all SATA power management features
• Internal DMA engine per port
• Hardware-assisted native command queuing (NCQ) for up to 32 entries
• 32-bit addressing
• Supports port multiplier with command-based switching
• Activity LED support
• Mechanical presence switch
• Cold presence detect
6.13.1 SATA Register Descriptions
Table 6-41 is a list of the SATA Controller registers.
BYTE ADDRESS
0x01E1 8000
0x01E1 8004
0x01E1 8008
0x01E1 800C
0x01E1 8010
0x01E1 8014
0x01E1 8018
0x01E1 80A0
0x01E1 80A4
0x01E1 80A8
0x01E1 80AC
0x01E1 80B0
0x01E1 80E0
0x01E1 80E8
0x01E1 80EC
0x01E1 80F0
0x01E1 80F4
0x01E1 80F8
0x01E1 80FC
0x01E1 8100
0x01E1 8108
0x01E1 8110
Table 6-41. SATA Controller Registers
ACRONYM
CAP
GHC
IS
PI
VS
CCC_CTL
CCC_PORTS
BISTAFR
BISTCR
BISTFCTR
BISTSR
BISTDECR
TIMER1MS
GPARAM1R
GPARAM2R
PPARAMR
TESTR
VERSIONR
IDR
P0CLB
P0FB
P0IS
REGISTER DESCRIPTION
HBA Capabilities Register
Global HBA Control Register
Interrupt Status Register
Ports Implemented Register
AHCI Version Register
Command Completion Coalescing Control Register
Command Completion Coalescing Ports Register
BIST Active FIS Register
BIST Control Register
BIST FIS Count Register
BIST Status Register
BIST DWORD Error Count Register
BIST DWORD Error Count Register
Global Parameter 1 Register
Global Parameter 2 Register
Port Parameter Register
Test Register
Version Register
ID Register
Port Command List Base Address Register
Port FIS Base Address Register
Port Interrupt Status Register
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Peripheral Information and Electrical Specifications 129