OMAP-L138_10 Datasheet, PDF (160/268 Pages) Texas Instruments – Low-Power Applications Processor

OMAP-L138 Low-Power Applications Processor
SPRS586A – JUNE 2009 – REVISED AUGUST 2009
Table 6-66. Additional SPI0 Slave Timings, 4-Pin Enable Option ^(1)(2)(3)
NO.
PARAMETER
Delay from final
24
t_{d(SPC_ENAH)S}
SPI0_CLK edge to
slave deasserting
SPI0_ENA.
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
1.2V
MIN
MAX
1.1V
MIN
MAX
1.5P-3
2.5P+17.5
1.5P-3
2.5P+20
– 0.5M+1.5P-3
–
0.5M+2.5P+17.
5
– 0.5M+1.5P-3
–
0.5M+2.5P+20
1.5P-3
2.5P+17.5
1.5P-3
2.5P+20
– 0.5M+1.5P-3
–
0.5+2.5P+17.5
– 0.5M+1.5P-3
– 0.5+2.5P+20
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1.0V
MIN
MAX
1.5P-3
2.5P+27
UNIT
– 0.5M+1.5P-3
–
0.5M+2.5P+27
ns
1.5P-3
2.5P+27
– 0.5M+1.5P-3 – 0.5+2.5P+27
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-62).
(2) P = SYSCLK2 period; M = t_c(SPC)M (SPI master bit clock period)
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
160 Peripheral Information and Electrical Specifications
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