OMAP-L138_10 Datasheet, PDF (36/268 Pages) Texas Instruments – Low-Power Applications Processor

OMAP-L138 Low-Power Applications Processor
SPRS586A – JUNE 2009 – REVISED AUGUST 2009
www.ti.com
Table 3-9. DDR2 Controller (DDR2) Terminal Functions (continued)
DDR_DQS[0]
DDR_DQS[1]
DDR_BA[2]
DDR_BA[1]
DDR_BA[0]
SIGNAL
NAME
DDR_DQGATE0
DDR_DQGATE1
DDR_ZP
DDR_VREF
DDR_DVDD18
TYPE ⁽¹⁾
NO.
T14
I/O
V11
I/O
U8
O
T9
O
V8
O
R11
O
R12
I
U12
O
R6
I
N6, N9, N10,
P7, P8, P9,
P10, R7, R8,
R9
PWR
PULL ⁽²⁾
DESCRIPTION
IPD
DDR2 data strobe inputs/outputs
IPD
IPD
IPD DDR2 SDRAM bank address
IPD
DDR2 loopback signal for external DQS gating.
IPD Route to DDR and back to DDR_DQGATE1 with
same constraints as used for DDR clock and data.
DDR2 loopback signal for external DQS gating.
IPD Route to DDR and back to DDR_DQGATE0 with
same constraints as used for DDR clock and data.
DDR2 reference output for drive strength calibration
—
of N and P channel outputs. Tie to ground via 50
ohm resistor @ 0.5% tolerance.
DDR voltage input for the DDR2/mDDR I/O buffers.
—
Note even in the case of mDDR an external resistor
divider connected to this pin is necessary.
—
DDR PHY 1.8V power supply pins
36
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