OMAP-L138_10 Datasheet, PDF (144/268 Pages) Texas Instruments – Low-Power Applications Processor

OMAP-L138 Low-Power Applications Processor
SPRS586A – JUNE 2009 – REVISED AUGUST 2009
www.ti.com
Table 6-53. Switching Characteristics for McBSP0 [1.0V]⁽¹⁾⁽²⁾
(see Figure 6-33)
NO.
PARAMETER
1.0V
MIN
MAX
UNIT
1
t_{d(CKSH-CKRXH)}
Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from
CLKS input
3
21.5
ns
2 t_c(CKRX)
3 t_w(CKRX)
4 t_d(CKRH-FRV)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
Delay time, CLKR high to internal FSR valid
CLKR/X int
2P or
26.6 ^{(3) (4) (5)}
ns
CLKR/X int
C - 2⁽⁶⁾
C + 2⁽⁶⁾
ns
CLKR int
-4
10
ns
CLKR ext
2.5
21.5
9 t_d(CKXH-FXV) Delay time, CLKX high to internal FSX valid
CLKX int
-4
CLKX ext
2.5
10
ns
21.5
12
t_{dis(CKXH-DXHZ)}
Disable time, DX high impedance following last data bit from CLKX
high
CLKX int
CLKX ext
13 t_d(CKXH-DXV) Delay time, CLKX high to DX valid
CLKX int
CLKX ext
14 t_d(FXH-DXV)
Delay time, FSX high to DX valid
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
FSX int
FSX ext
-4
10
ns
-2
21.5
-4 + D1⁽⁷⁾ 10 + D2⁽⁷⁾
2.5 + D1⁽⁷⁾ 21.5 + D2^{(7) ns}
-4 ⁽⁸⁾
5 ⁽⁸⁾
-2 ⁽⁸⁾
21.5 ⁽⁸⁾
ns
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) Minimum delay times also represent minimum output hold times.
(3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
(4) P = AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(5) Use whichever value is greater.
(6) C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = ASYNC period)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).
(7) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
(8) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
Table 6-54. Timing Requirements for McBSP1 [1.2V, 1.1V]⁽¹⁾ (see Figure 6-33)
NO.
PARAMETER
2 t_c(CKRX)
3 t_w(CKRX)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
5
t_su(FRH-CKRL)
Setup time, external FSR high before CLKR
low
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
1.2V
MIN
2P or 20 ⁽²⁾⁽³⁾
P - 1⁽⁵⁾
15
5
MAX
1.1V
MIN
2P or 25⁽²⁾⁽⁴⁾
P - 1⁽⁶⁾
18
5
MAX
UNIT
ns
ns
ns
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) P = AYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements.
(4) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements.
(5) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
(6) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
144 Peripheral Information and Electrical Specifications
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