OMAP-L138_10 Datasheet, PDF (15/268 Pages) Texas Instruments – Low-Power Applications Processor

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OMAP-L138 Low-Power Applications Processor
SPRS586A – JUNE 2009 – REVISED AUGUST 2009
3.5 DSP Subsystem
The DSP Subsystem includes the following features:
• C674x DSP CPU
• 32KB L1 Program (L1P)/Cache (up to 32KB)
• 32KB L1 Data (L1D)/Cache (up to 32KB)
• 256KB Unified Mapped RAM/Cache (L2)
• 1MB Mask-programmable ROM
• Little endian
32K Bytes
L1P RAM/
Cache
256
256K Bytes
L2 RAM
256
1M Byte
L2 ROM
256
256
Cache Control
Memory Protect L1P
Bandwidth Mgmt
Cache Control
Memory Protect L2
Bandwidth Mgmt
256
256
Instruction Fetch
C674x
Fixed/Floating Point CPU
Register
File A
64
Register
File B
64
256
IDMA
256
256
Power Down
Interrupt
Controller
Bandwidth Mgmt
Memory Protect L1D
Cache Control
EMC
CFG
MDMA
SDMA
8 x 32
64
64 64
64
32K Bytes
L1D RAM/
Cache
High
Performance
Switch Fabric
32 ^{Configuration}
Peripherals
Bus
Figure 3-1. C674x Megamodule Block Diagram
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