TMS320C4X Datasheet, PDF (553/726 Pages) Texas Instruments – Digital Signal Processing Solutions

LSH3 Logical Shift, 3 Operands
Description
Status Bits
Mode Bit
Cycles
Example
The seven LSBs of the src_count operand constitute the 2s-complement shift
count.
If count is greater than 0, a copy of the src operand is left-shifted by the value
of count, and the result is written to the dst (the src is not changed). Low-order
bits shifted in are zero-filled, and high-order bits are shifted out through the C
(carry) bit.
Logical left-shift:
C ← src ← 0
If count is less than 0, the src operand is right-shifted by the absolute value of
count. The high-order bits of the dst operand are zero-filled as shifted to the
right. Low-order bits are shifted out through the C (carry) bit.
Logical right-shift:
0 → src → C
If count is 0, no shift is performed and the C (carry) bit is set to 0.
If count is greater than 32, the carry (C) bit is set to the LSB. If count is less
than 32, the carry bit is cleared to 0. This also applies to LSH.
The src_count operand is assumed to be a signed integer. The src and dst op-
erands are assumed to be unsigned integers.
If ST (SET COND) = 0 and the destination register is R0 – R11, the condition
flags are modified. If ST (SET COND) = 1, they are modified for all destination
registers.
LUF Unaffected
LV Unaffected
UF 0
N MSB of the output
Z 1 if a zero output is generated, 0 otherwise
V0
C Set to the value of the last bit shifted out. 0 for a shift count of 0
OVM operation is not affected by OVM bit value.
1
None
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