TMS320C4X Datasheet, PDF (352/726 Pages) Texas Instruments – Digital Signal Processing Solutions

DMA Memory Transfer Timing
11.11 DMA Memory Transfer Timing
The ’C4x provides six DMA channels (twelve DMA channels if they are all in
split mode) with a fixed/rotating priority arbitration scheme and configurable
CPU/DMA priority scheme (for detailed information, see Section 11.6 for DMA
internal priority schemes and Section 11.7, CPU and DMA Coprocessor Ar-
bitration, for CPU and DMA priority arbitration).
The maximum data transfer rate that the ’C4x DMA sustains is one word every
two cycles. The six DMA channels transfer data in a sequential time-slice fash-
ion, rather than simultaneously, because they share common buses.
DMA memory transfer timing can be very complicated, especially if bus re-
source conflicts occur. However, some rules help you calculate the transfer
timing for certain DMA setups. For simplification, the following subsection fo-
cuses on a single-channel DMA memory transfer timing with no conflict with
the CPU or other DMA channels. You can obtain the actual DMA transfer tim-
ing by combining the calculations for single-channel DMA transfer timing with
those for bus resource conflict situations.
11.11.1 Single DMA Memory Transfer Timing
When the DMA memory transfer has no conflict with the CPU or any other
DMA channels, the number of cycles of a DMA transfer depends on whether
the source and destination location are designated as on-chip memory, pe-
ripheral, or external ports. When the external port is used, the DMA transfer
speed is affected by two factors: the external bus wait state and the read/write
conflict (for example, if a write is followed by a read, the read takes two cycles).
Figure 11–31 through Figure 11–33 show the number of cycles a DMA transfer
requires from different sources to different destinations. Entries in the table
represents the number of cycles required to do the T transfers, assuming that
there are no pipeline conflicts. A timing diagram for the DMA transfers accom-
panies each figure.
The DMA Coprocessor
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