TMS320C4X Datasheet, PDF (434/726 Pages) Texas Instruments – Digital Signal Processing Solutions

Syntax
Operands
Opcode
Word Fields
Operation
Description
Status Bits
Mode Bit
Cycles
Absolute Value of Integer ABSI
ABSI src, dst
src: general-addressing modes
dst: register (any register in CPU primary-register file)
31
24 23
16 15
87
0
000 00 0 0 01 G
dst
src
G
src addressing modes
00
register (any register in
CPU primary-register file)
01
direct
10
indirect
11
immediate
|src| → dst
The absolute value of the src operand is loaded into the dst register. The src
and dst operands are assumed to be signed integers.
An overflow occurs if src = 8000 0000h. If ST(OVM) = 1, the result is
dst = 7FFF FFFFh. If ST(OVM) = 0, the result is dst = 8000 0000h.
If ST (SET COND) = 0 and the destination register is R0 – R11, the condition
flags are modified. If ST (SET COND) = 1, they are modified for all destination
registers.
LUF Unaffected
LV 1 if an integer overflow occurs, unchanged otherwise
UF 0
N0
Z 1 if a zero result is generated, 0 otherwise
V 1 if an integer overflow occurs, 0 otherwise
C Unaffected
OVM operation is affected by OVM bit value.
1
Assembly Language Instructions
14-29