TMS320C4X Datasheet, PDF (198/726 Pages) Texas Instruments – Digital Signal Processing Solutions

Reset
Table 7–3. Pin States After System Reset (Continued)
(e) Communication Port 3 Interface (12 pins)
Signal
C3D(7– 0)
Pins
8
I/O^§ Type^† Description
I/O
S Set to high-impedance
CACK3
1
I/O
A Set to high-impedance
CRDY3
CREQ3
CSTRB3
1
I/O
A
Set high-impedance when reset goes low
and then set to one when reset goes high
1
I/O
A
Set high-impedance when reset goes low
and then set to one when reset goes high
1
I/O
A Set to high-impedance
(f) Communication Port 4 Interface (12 pins)
Signal
Pins I/O^§ Type^† Description
C4D(7– 0) 8
I/O
S Set to high-impedance
CACK4
1
I/O
A Set to high-impedance
CRDY4
CREQ4
1
I/O
A
Set high-impedance when reset goes low
and then set to one when reset goes high
1
I/O
A
Set high-impedance when reset goes low
and then set to one when reset goes high
CSTRB4
1 I/O
A Set to high-impedance
(g) Communication Port 5 Interface (12 pins)
Signal
Pins I/O^§ Type^† Description
C5D(7– 0) 8
I/O
S Set to high-impedance
CACK5
1
I/O
A Set to high-impedance
CRDY5
1
I/O
A
Set high-impedance when reset goes low
and then set to one when reset goes high
CREQ5
1
I/O
A
Set high-impedance when reset goes low
and then set to one when reset goes high
CSTRB5
1 I/O
A Set to high-impedance
† _{A = Asynchronous, S = Synchronous}
‡ _{Recommended decoupling capacitors are one multiple 0.1 µF and 4.7 µF around the device.}
Number depends on specific board noise conditions.
§ _{I=Input, O=Output, Z=High-impedance state.}
Program Flow Control
7-31