TMS320C4X Datasheet, PDF (304/726 Pages) Texas Instruments – Digital Signal Processing Solutions

DMA Functional Description
11.2 DMA Functional Description
The DMA coprocessor supports six DMA channels that perform transfers to
and from anywhere in the ’C4x memory map.
Each DMA channel is controlled by nine registers that are mapped in the ’C4x
peripheral address space, as shown in Figure 11–1. The major DMA registers
are described in Section 11.3.
The DMA coprocessor has dedicated on-chip address and data buses (see
Figure 2–8 for a block diagram of the peripherals of the ’C4x). All accesses
made by the six DMA channels are arbitrated in the DMA coprocessor and take
place over these dedicated buses. The six DMA channels transfer data in a
sequential time-slice fashion, rather than simultaneously, because they share
common buses.
The DMA channels can run constantly or can be triggered by external
(IIOF3–0) or internal (on-chip timers and communication ports) interrupts.
The DMA coprocessor can transfer data in a bit-reversed fashion (for FFT ap-
plications) or in a linear fashion; it can also transfer matrix data in a row or col-
umn fashion.
The DMA coprocessor has two basic operational modes:
- Unified Mode: Used for memory-to-memory transfers. The unified mode
is described in Section 11.4, DMA Unified Mode. The unified block transfer
sequence is presented in subsection 11.2.1, Block Transfer Sequence.
- Split Mode: Used for two-way, memory-to-communication port transfers.
The split mode is described in Section 11.5, DMA Split Mode.
The DMA Coprocessor
11-3