TMS320C4X Datasheet, PDF (441/726 Pages) Texas Instruments – Digital Signal Processing Solutions

ADDC3 Add Integer With Carry, 3 Operands
Description
Status Bits
Mode Bit
Cycles
Example
The sum of the src1 and src2 operands and value of the C (carry) flag is loaded
into the dst register. The src1, src2, and dst operands are assumed to be
signed integers.
If ST (SET COND) = 0, the condition flags are modified if the destination regis-
ter is R0 – R11. If ST (SET COND) = 1, they are modified for all destination
registers.
LUF Unaffected
LV 1 if an integer overflow occurs, unchanged otherwise
U0
N 1 if a negative result is generated, 0 otherwise
Z 1 if a zero result is generated, 0 otherwise
V 1 if an integer overflow occurs, 0 otherwise
C 1 if a carry occurs, 0 otherwise
OVM operation is affected by OVM bit value.
1
None
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