TLC34076 Datasheet, PDF (55/68 Pages) Texas Instruments – Video Interface Palette

3.6 Switching Characteristics (TLC34076C and TLC34076M) Over
Recommended Ranges of Supply Voltages and Operating Temperature
(Continued)
PARAMETER
Delay time, DOTCLK high to IOR/IOG/IOB active
td6 (analog output delay time) (see Note 10 and
Figure 3–2)
td7
Analog output settling time (see Note 11 and Figure
3–2)
-135
-170
MIN TYP^† MAX
MIN TYP^†
UNIT
MAX
20
20
ns
6
5
ns
td8
Delay time, DOTCLK high to HSYNCOUT and
VSYNCOUT valid (see Figure 3–2)
3
3
ns
tw6
Pulse duration, SCLK high (see Note 8 and
Figure 3–3)
15
55
ns
Pixel data latching frequency (see Note 12)
110 MHz
tr
Rise time at HSYNCOUT Analog output
(see Note 13 and Figure 3–2)
2
2
ns
Analog output skew
0
2
0
2 ns
† _{All typical values are at VDD = 5 V, TA = 25°C.}
8. This parameter applies when the split shift-register transfer (SSRT) function is enabled (see subsection
2.9.1 for details).
10. Measured from the 90% point of the rising edge of DOTCLK to 50% of the full-scale transition.
11. Measured from the 50% point of the full-scale transition to the point at which the output has settled, within
± 1 LSB (settling time does not include clock and data feedthrough).
12. SCLK can be programmed to latch pixel data at the input port up to this limit. However, the SCLK output
buffer can only be used up to the SCLK frequency limit of 85 MHz.
13. Measured between 10% and 90% of the full-scale transition.
3–11