TLC34076 Datasheet, PDF (40/68 Pages) Texas Instruments – Video Interface Palette

2.11.4 Sync Enable Control (Bit 5)
Bit 5 specifies whether or not sync information is to be output onto IOG (see Table 2–11). Bit settings are:
• 0 = Disable sync (default)
• 1 = Enable sync
2.11.5 Little-Endian and Big-Endian Mode Control (Bit 6)
Bit 6 specifies either little-endain or big-endian data format for the pixel bus frame-buffer interface (see
subsection 2.7.1). Settings are :
• 0 = little endian (default)
• 1 = big endian
2.11.6 MUXOUT (Bit 7)
Bit 7 indicates to external circuitry that the device is running in VGA pass-through mode. The MUXOUT bit
does not affect the operation of the device (see Section 2.10). Bit settings are:
• 0 = MUXOUT is low (default in VGA pass-through mode)
• 1 = MUXOUT is high
2.12 Test Register
There are three test functions provided in the TLC34076, and they are all controlled and monitored through
the test register. The three test functions are:
• Data flow check
• DAC analog test
• Screen integrity test
The test register has two ports: one for a control word that is accessed by writing to the register location,
and one for the data word that is accessed by reading from the register location. Depending on the channel
written in the control word, the data read presents the information for that channel.
The control word is 3 bits long and occupies D2 – D0 bit positions. It specifies which of the eight channels
to inspect. Table 2–12 and state machine diagrams (see Figure 2–11) show how each channel is addressed.
Table 2–12. Test Mode Selection
D2 D1 D0
CHANNEL
0 0 0 Color palette red value
0 0 1 Color palette green value
0 1 0 Color palette blue value
0 1 1 Identification code
1 0 0 Ones-accumulation red value
1 0 1 Ones-accumulation green value
1 1 0 Ones-accumulation blue value
1 1 1 Analog test
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