TLC34076 Datasheet, PDF (35/68 Pages) Texas Instruments – Video Interface Palette

A resistor (R_SET) is needed to connect FS ADJUST to GND to control the magnitude of the full-scale video
signal. The IRE relationships in Figures 2–7 and 2– 8 are maintained regardless of the full-scale output
current.
The relationship between R_SET and the full-scale output current IOG is:
R_SET (Ω) = K1 × V_REF (V) / IOG (mA)
The full-scale output current on IOR and IOB for a given R_SET is:
IOR, IOB (mA) = K2 × V_REF (V) / R_SET (Ω)
where K1 and K2 are defined as:
IRE LEVEL
IOG
8-BIT OUTPUT 6-BIT OUTPUT
IOR, IOB
8-BIT OUTPUT 6-BIT OUTPUT
7.5-IRE
K1 = 11,294
K1 = 11,206
K2 = 8,067
K2 = 7,979
0-IRE
K1 = 10,684
K1 = 10,600
K2 = 7,462
K2 = 7,374
2.7 Frame-Buffer Interface with Little-Endian and Big-Endian Modes
The TLC34076 provides two clock signals for controlling the frame-buffer interface. They are SCLK and
VCLK. SCLK can clock out data directly from the VRAM shift registers. Split shift-register transfer
functionality is also supported. VCLK clocks and synchronizes control inputs like HSYNC, VSYNC, and
BLANK.
The pixel data presented at the inputs is latched at the rising edge of SCLK in normal mode or the rising edge
of CLK0 in VGA pass-through mode. Control inputs HSYNC, VSYNC, and BLANK are sampled and latched
at the falling edge of VCLK in normal mode, while HSYNC, VSYNC, and VGABLANK are latched at the rising
edge of CLK0 in VGA pass-through mode. Both data and control signals are lined up at the DAC outputs
to the monitor through the internal pipeline delay, so external glue logic is not required. The outputs of the
DACs are capable of directly driving a 37.5-Ω load, as in the case of a doubly terminated 75-Ω cable (see
Figures 2–7 and 2– 8 for nominal output levels).
The frame-buffer interface (pixel bus) supports both little-endian and big-endian data formats for all normal
multiplexing and true-color modes of operation. The data-format mode select is controlled by General
Control register bit 6 (see Section 2.11). When GCR bit 6 is cleared to 0 (default), the format is set to the
little-endian mode. When GCR bit 6 is set to 1, the format is set to the big-endian mode.
In a big-endian mode design the external VRAM data bus bits must be connected in reverse order to the
TLC34076 pixel bus (i.e. D31 connected to P0, and D0 connected to P31, etc.). This ensures that the least
significant channel always provides the first pixel to be displayed in the normal multiplexing modes.
2.8 HSYNC, VSYNC, and BLANK
For the normal modes, HSYNC and VSYNC are active-low pulses, and they are passed through
true/complement gates to the HSYNCOUT and VSYNCOUT outputs. The output polarities of HSYNCOUT
and VSYNCOUT can be programmed through the general control register. However, for the VGA
pass-through mode, the polarities needed for monitors are already provided at the feature connector from
which HSYNC and VSYNC are sourced, so the TLC34076 passes HSYNC and VSYNC through to
HSYNCOUT and VSYNCOUT without polarity change. As described in Section 2.3 and Figures 2– 2
through 2– 5, the BLANK, HSYNC, and VSYNC inputs are sampled and latched on the falling edge of VCLK
in the normal modes, and they are latched on the rising edge of the CLK0 input in the VGA pass-through
mode (see Figure 3– 2 for the detailed timing).
2–19