TLC34076 Datasheet, PDF (31/68 Pages) Texas Instruments – Video Interface Palette

P0 – P15 is executed first, while the word latched on P16 – P31 is executed last. The user should program
the SCLK divide ratio in the output-clock selection register to divide by two (see Table 2–8 for the exact bit
definitions).
Mode 6d is a multiplexed version of mode 6b that allows two 16-bit XGA-compatible words to be latched
into the TLC34076 pixel port with one SCLK. In this mode, the 16-bit word latched on pixel port inputs
P0 – P15 is executed first, while the word latched on P16 – P31 is executed last. The user should program
the SCLK divide ratio in the output-clock selection register to divide by 2 (see Table 2–8 for the bit definitions).
Mode 6e is a 24-bit true-color mode that features 8 bits of data for each color, as well as 8 bits of overlay
information. The order in which the color and overlay fields appear in the 32-bit word are the reverse of
mode 6f (see Table 2–8 for the bit definitions).
Mode 6f is the 24-bit true-color mode used on the TLC34076. It also features 8 bits of data for each color,
as well as 8 bits of overlay information (see Table 2–8 for the bit definitions).
Since only 5 bits (6 bits for green in mode 6b and 6d) are provided for each color in the 16-bit true-color
modes (6a–6d), the color data is internally shifted by the TLC34076 to the five MSB positions (six MSB
positions for green in modes 6b and 6d) before being presented to the 3-color DACs. The remaining lower
3 bits (lower 2 bits for green in modes 6b and 6d) then clear to 0.
When in true-color modes 6a or 6c, the internal palette page register fills the remaining seven MSBs of
overlay data (see subsection 2.2.3). This occurs in these modes because there is only 1 bit of overlay
information presented in the true-color word. In order to enable the true-color data to the DACs, all 8 overlay
bits must be reset to 0. This can be accomplished by either writing zeros to the internal palette page register
and the overlay bit, or by writing zeros to the internal read mask (see subsection 2.4.6).
When in true-color modes 6e or 6f, the data input only works in the 8-bit mode. In other words, when only
6 bits are to be used, the two LSB inputs for each color must be tied to GND. However, the palette, which
is used by the overlay input, is still governed by 8/6-input terminal and the output multiplexer (MUX) selects
8-bit data or 6-bit data accordingly. The 8/6-input terminal is also valid in the other 16-bit modes as well.
Both little-endian (default) and big-endian data formats are supported by the true-color modes (see
subsection 2.6.1 and Table 2–8 for more information).
2.4.5 Multiplex Control Register
The MUX is controlled using the 8-bit mux control register. The bit fields of the register are in Table 2– 6 and
Table 2–7.
As an example of how to use Table 2– 6, suppose that the design goals specify a system with 8 data bits
per pixel and the lowest possible SCLK rate. Table 2– 6 shows that, for non-VGA pass-through operation,
only mode 4 supports an 8-bit pixel depth. The lowest possible SCLK rate within mode 4 is 1:4. This set of
conditions are selected by writing the value 1Eh to the mux control register. The pixel latching sequence
column shows that, in this mode, pixel-input ports P7 – P0 should be connected to the earliest displayed
pixel plane, followed by P15 – P8, P23 – P16, and then P31 – P24 as the last displayed pixel plane. Assuming
that VCLK is programmed as DOTCLK/4, Table 2– 5 shows that the 1:4 SCLK ratio is selected by writing
the value 12h to the output clock selection register. The special nibble mode should also be disabled (see
subsections 2.9.2 and 2.11.2).
When the mux control register is loaded with 2Dh, the TLC34076 enters the VGA pass-through mode which
is the same condition as the default power-up mode. More details are given in subsection 2.5.4.
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