TLC34076 Datasheet, PDF (52/68 Pages) Texas Instruments – Video Interface Palette

3.5.2 Timing Requirements for TLC34076M Over Recommended Ranges of Supply
Voltages and Operating Temperature (see Note 5)
MIN NOM MAX UNIT
Dot-clock frequency
135 MHz
CLK0 frequency for VGA pass-through mode
85 MHz
tc
Cycle time, CLK0 – CLK3 (see Figure 3–2)
TTL
7.4
ns
ECL
7.4
tsu1 Setup time, RS0 – RS3 valid before RD or WR↓ (see Figure 3–1)
10
ns
th1 Hold time, RS0 – RS3 valid after RD or WR low (see Figure 3–1)
10
ns
tsu2 Setup time, D0 – D7 valid before WR↑ (see Figure 3–1)
35
ns
th2 Hold time, D0 – D7 valid after WR high (see Figure 3–1)
0
ns
tsu3
Setup time, VGA0 – VGA7 and HSYNC, VSYNC, and VGABLANK valid
before CLK0-CLK3↑ (see Figure 3–2)
2
ns
th3
Hold time, VGA0 – VGA7 and HSYNC, VSYNC, and VGABLANK valid
after CLK0 high (see Figure 3–2)
2
ns
tsu4 Setup time, P0 – P31 valid before SCLK↑ (see Figure 3–2)
0
ns
th4 Hold time, P0 – P31 valid after SCLK high (see Figure 3–2)
8
ns
tsu5
Setup time, HSYNC, VSYNC, and BLANK valid before VCLK↓ (see
Figure 3–2)
5
ns
th5
Hold time, HSYNC, VSYNC, and BLANK valid after VCLK low (see
Figure 3–2)
2
ns
tw1 Pulse duration, RD or WR low (see Figure 3–1)
tw2 Pulse duration, RD or WR high (see Figure 3–1)
tw3 Pulse duration, CLK0 – CLK3 high (see Figure 3–2)
50
ns
30
ns
TTL
3
ns
ECL
3
TTL
tw4 Pulse duration, CLK0 – CLK3 low (see Figure 3–2)
ECL
3
ns
3
tw5 Pulse duration, SFLAG/NFLAG high (see Note 6 and Figure 3–3)
30
ns
† _{All typical values are at VDD = 5 V, TA = 25°C.}
NOTES: 5. TTL input signals are 0 to 3 V with less than 3 ns rise/fall time between the 10% and 90% levels, unless
otherwise specified. ECL input signals are VDD –1.8 V to VDD – 0.8 V with less than 2 ns rise/fall time
between the 20% and 80% levels. For input and output signals, timing reference points are at the 10% and
90% signal levels. Analog output loads are less than 10 pF. D0 – D7 output loads are less than 50 pF. All
other output loads are less than 50 pF, unless otherwise specified.
6. This parameter applies when the split shift register transfer (SSRT) function is enabled (see subsection
2.9.1 for details).
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