TLC34076 Datasheet, PDF (26/68 Pages) Texas Instruments – Video Interface Palette

MODE
3
Table 2–6. Mode and Bus Width Selection (Continued)
MUX CONTROL REGISTER BITS^†
5
4
3
2
1
0
DATA BITS
PER
PIXEL BUS
PIXEL^‡
WIDTH
SCLK
DIVIDE
RATIO^§
0
1
1
0
0
0
4
4
1
0
1
1
0
0
1
4
8
2
0
1
1
0
1
0
4
16
4
0
1
1
0
1
1
4
32
8
PIXEL
LATCHING
SEQUENCE^¶
1) P3 – P0
1) P3 – P0
2) P7 – P4
1) P3 – P0
2) P7 – P4
3) P11 – P8
4) P15 – P12
1) P3 – P0
2) P7 – P4
8) P31 – P28
0
1
1
1
0
0
8
8
1
1) P7 – P0
0
1
1
1
0
1
8
16
2
1) P7 – P0
2) P15 – P8
4
0
1
1
1
1
0
8
32
4
1) P7 – P0
2) P15 – P8
3) P23 – P16
4) P31 – P24
† _{Bits 6 and 7 are don’t care bits.}
‡ _{This is the number of bits of pixel port (or VGA port in mode 1) information used as color data for each displayed pixel,}
often referred to as the number of bit-planes. This may be color palette address data (modes 0 – 5) or DAC data
(mode 6).
§ _{The SCLK divide ratio is the number used for the output clock selection register. It indicates the number of pixels per}
bus load, or the number of pixels associated with each SCLK pulse. For example, with a 32-bit pixel bus width and 8
bit-planes, four pixels comprise each bus load. The SCLK divide ratio is not automatically set by mode selection, but
must be written to the output clock selection register.
¶ _{For each operating mode, the pixel latching sequence indicates the sequence in which pixel port or VGA port data are}
latched into the device. The latching sequence is initiated by a rising edge on SCLK. For modes in which multiple groups
of data are latched, the SCLK rising edge latches all the groups, and the pixel clock shifts them out starting with the
low-numbered group. For example, in mode 3 with a 16-bit pixel bus width, the rising edge of SCLK latches all the data
groups, and the pixel clock shifts them out in the order P3 – P0, P7 – P4, P11 – P8, P15 – P12.
NOTE 1: Although leaving unused pins floating does not adversely affect device operation, tying unused pins to ground
lowers power consumption and, thus, is recommended.
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