TLC34076 Datasheet, PDF (22/68 Pages) Texas Instruments – Video Interface Palette

2.3.2 VCLK
The VCLK frequency can be selected to be 1:1, 1:2, 1:4, 1:8, 1:16, or 1:32 of that of the dot clock, or it can
be held at a high logic level, which is the VCLK default condition. VCLK is not used in VGA pass-through
mode.
VCLK is used by a GSP or custom-designed control logic to generate control signals (BLANK, HSYNC, and
VSYNC). As can be seen from Figures 2– 2, 2– 3, 2– 4, and 2– 5, since the control signals are sampled by
VCLK, it is obvious that VCLK has to be enabled.
VCLK
BLANK
at Input Terminal
Load
(Internal Signal
for Data Latch)
Blank
(Internal Signal
Before DOTCLK
Pipeline Delay)
Pixel Data
at Input Terminal
Latch Last Group
of Pixel Data
Latch First Group
of Pixel Data
Latch Last Group
of Pixel Data
Last Group of Pixel Data
1st
Group
G2rnodupG3rrodupG4rtohupG5rtohup
6th
Group
SCLK
NOTE A: Either the SSRT function is disabled (general control register bit 2 = 0), or the SFLAG/NFLAG input is held
low when the SSRT function is enabled (general-control register bit 2 = 1).
Figure 2–2. SCLK/VCLK Control Timing (SSRT Disabled,
SCLK Frequency = VCLK Frequency)
2–6