OMAP3503DCBBA Datasheet, PDF (54/264 Pages) Texas Instruments – OMAP3515 and OMAP3503 Applications Processors

OMAP3515, OMAP3503
SPRS505H – FEBRUARY 2008 – REVISED OCTOBER 2013
www.ti.com
Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾ (continued)
BALL
BALL TOP PIN NAME
BOTTOM [1]
[2]
[3]
MODE [4]
P19
NA
mmc1_dat7
0
gpio_129
4
safe_mode
7
J25
NA
i2c1_scl
0
J24
NA
i2c1_sda
0
C2
NA
i2c2_scl
0
gpio_168
4
safe_mode
7
C1
NA
i2c2_sda
0
gpio_183
4
safe_mode
7
AB4
NA
i2c3_scl
0
gpio_184
4
safe_mode
7
AC4
NA
i2c3_sda
0
gpio_185
4
safe_mode
7
U19
NA
mcbsp1_clkr
0
mcspi4_clk
1
gpio_156
4
safe_mode
7
T17
NA
mcbsp1_clkx
0
mcbsp3_clkx
2
gpio_162
4
safe_mode
7
T20
NA
mcbsp1_dr
0
mcspi4_somi
1
mcbsp3_dr
2
gpio_159
4
safe_mode
7
U17
NA
mcbsp1_dx
0
mcspi4_simo
1
mcbsp3_dx
2
gpio_158
4
safe_mode
7
V17
NA
mcbsp1_fsr
0
cam_global_r
2
eset
gpio_157
4
safe_mode
7
P20
NA
mcbsp1_fsx
0
mcspi4_cs0
1
mcbsp3_fsx
2
gpio_161
4
safe_mode
7
TYPE [5]
IO
IO
-
IOD
IOD
IOD
IO
-
IOD
IO
-
IOD
IO
-
IOD
IO
-
IO
IO
IO
-
IO
IO
IO
-
I
IO
I
IO
-
IO
IO
IO
IO
-
IO
IO
IO
-
IO
IO
IO
IO
-
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
RESET REL.
MODE [8]
POWER [9]
L
L
7
vdds_mmc1a
HYS [10]
No
BUFFER
STRENG TH
(mA) [11]
8
PULLUP
/DOWN
TYPE [12]
PU/PD ⁽⁸⁾
IO CELL [13]
LVCMOS
H
H
0
vdds
Yes
3
PU100/ Open Drain
PD100
H
H
0
vdds
Yes
3
PU100/ Open Drain
PD100
H
H
7
vdds
Yes
3
PU100/ Open Drain
PD100
4
4
H
H
7
vdds
Yes
3
PU100/ Open Drain
PD100
4
4
H
H
7
vdds
Yes
3
PU100/ Open Drain
PD100
4
4
H
H
7
vdds
Yes
3
PU100/ Open Drain
PD100
4
4
L
L
7
vdds
Yes
4 ⁽⁹⁾
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
4 ⁽⁹⁾
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
4 ⁽⁹⁾
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
4 ⁽⁹⁾
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
4 ⁽⁹⁾
PU100/
LVCMOS
PD100
L
L
7
vdds
Yes
4 ⁽⁹⁾
PU100/
LVCMOS
PD100
(9) The capacity load range is [2 pf to 6 pF].
54
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