OMAP3503DCBBA Datasheet, PDF (153/264 Pages) Texas Instruments – OMAP3515 and OMAP3503 Applications Processors

OMAP3515, OMAP3503
www.ti.com
SPRS505H – FEBRUARY 2008 – REVISED OCTOBER 2013
6 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
6.1 Timing Test Conditions
All timing requirements and switching characteristics are valid over the recommended operating conditions
of , unless otherwise specified.
6.2 Interface Clock Specifications
6.2.1 Interface Clock Terminology
The Interface clock is used at the system level to sequence the data and/or control transfers accordingly
with the interface protocol.
6.2.2 Interface Clock Frequency
The two interface clock characteristics are:
• The maximum clock frequency
• The maximum operating frequency
The interface clock frequency documented in this document is the maximum clock frequency, which
corresponds to the maximum frequency programmable on this output clock. This frequency defines the
maximum limit supported by the OMAP3515/03 IC and doesn’t take into account any system consideration
(PCB, peripherals).
The system designer will have to consider these system considerations and OMAP3515/03 IC timings
characteristics as well, to define properly the maximum operating frequency, which corresponds to the
maximum frequency supported to transfer the data on this interface.
6.2.3 Clock Jitter Specifications
Jitter is a phase noise, which may alter different characteristics of a clock signal. The jitter specified in this
document is the time difference between the typical cycle period and the actual cycle period affected by
noise sources on the clock. The cycle (or period) jitter terminology identifies this type of jitter.
Cycle (or Period) Jitter
T_n-1
T_n
T_n+1
Max. Cycle Jitter = Max (T_i)
Min. Cycle Jitter = Min (T_i)
Jitter Standard Deviation (or rms Jitter) = Standard Deviation (T_i)
030-020
Figure 6-1. Cycle (or Period) Jitter
6.2.4 Clock Duty Cycle Error
The duty cycle error is the ratio between either the high-level pulse duration or the low-level pulse duration
and the cycle time of a clock signal.
Copyright © 2008–2013, Texas Instruments Incorporated
TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 153
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