OMAP3503DCBBA Datasheet, PDF (38/264 Pages) Texas Instruments – OMAP3515 and OMAP3503 Applications Processors

OMAP3515, OMAP3503
SPRS505H – FEBRUARY 2008 – REVISED OCTOBER 2013
www.ti.com
Table 2-1. Ball Characteristics (CBB Pkg.)⁽¹⁾ (continued)
BALL
BALL TOP PIN NAME MODE [4] TYPE [5]
BOTTOM [1] [2]
[3]
uart1_cts 5
I
safe_mode 7
K26
NA
mcbsp1_fsx 0
IO
mcspi4_cs0 1
IO
mcbsp3_fsx 2
IO
gpio_161 4
IO
safe_mode 7
W21
NA
mcbsp1_ 0
IO
clkx
mcbsp3_ 2
IO
clkx
gpio_162 4
IO
safe_mode 7
H18
NA
uart3_cts_ 0
IO
rctx
gpio_163 4
IO
safe_mode 7
H19
NA
uart3_rts_ sd 0
O
gpio_164 4
IO
safe_mode 7
H20
NA
uart3_rx_ irrx 0
I
gpio_165 4
IO
safe_mode 7
H21
NA
uart3_tx_ irtx 0
O
gpio_166 4
IO
safe_mode 7
T28
NA
hsusb0_clk 0
I
gpio_120 4
IO
safe_mode 7
T25
NA
hsusb0_stp 0
O
gpio_121 4
IO
safe_mode 7
R28
NA
hsusb0_dir 0
I
gpio_122 4
IO
safe_mode 7
T26
NA
hsusb0_nxt 0
I
gpio_124 4
IO
safe_mode 7
T27
NA
hsusb0_
0
IO
data0
uart3_tx_ irtx 2
O
gpio_125 4
IO
safe_mode 7
U28
NA
hsusb0_
0
IO
data1
uart3_rx_ irrx 2
I
gpio_130 4
IO
safe_mode 7
U27
NA
hsusb0_
0
IO
data2
uart3_rts_ sd 2
O
gpio_131 4
IO
safe_mode 7
U26
NA
hsusb0_
0
IO
data3
uart3_cts_ 2
IO
rctx
gpio_169 4
IO
BALL
RESET
STATE [6]
BALL
RESET REL. POWER [9] HYS [10]
RESET REL. MODE [8]
STATE [7]
L
L
7
vdds
Yes
L
L
7
vdds
Yes
H
H
7
vdds
Yes
H
H
7
vdds
Yes
H
H
7
vdds
Yes
H
H
7
vdds
Yes
L
L
7
vdds
Yes
H
H
7
vdds
Yes
L
L
7
vdds
Yes
L
L
7
vdds
Yes
L
L
7
vdds
Yes
L
L
7
vdds
Yes
L
L
7
vdds
Yes
L
L
7
vdds
Yes
BUFFER PULLUP
STRENG TH /DOWN
(mA) [11] TYPE [12]
IO CELL [13]
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
4
PU/ PD
LVCMOS
38
TERMINAL DESCRIPTION
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