OMAP3503DCBBA Datasheet, PDF (234/264 Pages) Texas Instruments – OMAP3515 and OMAP3503 Applications Processors

OMAP3515, OMAP3503
SPRS505H – FEBRUARY 2008 – REVISED OCTOBER 2013
www.ti.com
6.7 Removable Media Interfaces
6.7.1 High-Speed Multimedia Memory Card (MMC) and Secure Digital IO Card (SDIO) Timing
The MMC/SDIO host controller provides an interface to high-speed and standard MMC, SD memory
cards, or SDIO cards. The application interface is responsible for managing transaction semantics. The
MMC/SDIO host controller deals with MMC/SDIO protocol at transmission level, packing data, adding
CRC, start/end bit, and checking for syntactical correctness.
There are three MMC interfaces on the OMAP3515/03:
• MMC/SD/SDIO Interface 1:
– 1.8 V/3 V support
– 8 bits
• MMC/SD/SDIO Interface 2:
– 1.8 V support
– 8 bits
– 4 bits with external transceiver allowing to support 3 V peripherals. Transceiver direction control
signals are multiplexed with the upper four data bits.
• MMC/SD/SDIO Interface 3:
– 1.8 V support
– 8 bits
6.7.1.1 MMC/SD/SDIO in SD Identification Mode
Table 6-118 and Table 6-119 assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 6-117. MMC/SD/SDIO Timing Conditions – SD Identification Mode
SD Identification Mode
Input Conditions
t_R
t_F
Output Conditions
C_LOAD
TIMING CONDITION PARAMETER
Input signal rise time
Input signal fall time
Output load capacitance
VALUE
10
10
40
UNIT
ns
ns
pF
Table 6-118. MMC/SD/SDIO Timing Requirements – SD Identification Mode^{(1) (2) (3)}
NO.
PARAMETER
SD Identification Mode
MMC/SD/SDIO Interface 1 (1.8 V IO)
HSSD3/SD3 t_{su(CMDV-CLKIH)}
Setup time, mmc1_cmd valid before
mmc1_clk rising clock edge
HSSD4/SD4 t_{su(CLKIH-CMDIV)}
Hold time, mmc1_cmd valid after
mmc1_clk rising clock edge
MMC/SD/SDIO Interface 1 (3.0 V IO)
HSSD3/SD3 t_{su(CMDV-CLKIH)}
Setup time, mmc1_cmd valid before
mmc1_clk rising clock edge
HSSD4/SD4 t_{su(CLKIH-CMDIV)}
Hold time, mmc1_cmd valid after
mmc1_clk rising clock edge
MMC/SD/SDIO Interface 2
1.15 V
MIN
MAX
1.0 V
MIN
MAX
UNIT
1198.4
1198.4
ns
1249.2
1249.2
ns
1198.4
1198.4
ns
1249.2
1249.2
ns
(1) Timing parameters are referred to output clock specified in Table 6-119.
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-119.
(3) Corresponding figures showing timing parameters are common with other interface modes. (See SD and HS SD modes).
234 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
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