MSP430F2618-EP Datasheet, PDF (51/92 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F2618- EP
MIXED SIGNAL MICROCONTROLLER
SLAS632 -- DECEMBER 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (UART mode)
f_USCI
PARAMETER
USCI input clock frequency
TEST CONDITIONS
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50%  10%
V_CC
MIN TYP MAX UNIT
f_SYSTEM MHz
f_BITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
2.2 V /3 V
1 MHz
UART receive deglitch time
t_
(see Note 1)
2.2 V
3V
50 150 600 ns
50 100 600 ns
NOTE 1: Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI master mode) (see Figure 27 and Figure 28)
f_USCI
PARAMETER
USCI input clock frequency
TEST CONDITIONS
SMCLK, ACLK
Duty cycle = 50%  10%
V_CC
MIN MAX UNIT
f_SYSTEM MHz
t_SU,MI
SOMI input data setup time
2.2 V
110
ns
3V
75
t_HD,MI
SOMI input data hold time
2.2 V
0
ns
3V
0
t_VALID,MO
SIMO output data valid time
UCLK edge to SIMO valid;
C_L = 20 pF
2.2 V
3V
30
ns
20
NOTE 1:
f_UCxCLK
=
1
2t_LO∕HI
with
t_LO∕HI
≥
max(t_{VALID,MO(USCI)}
+
t_{SU,SI(Slave),}
t_SU,MI(USCI)
+
t_{VALID,SO(Slave)}).
For the slave parameters t_SU,SI(Slave) and t_{VALID,SO(Slave)}, see the SPI parameters of the attached slave.
USCI (SPI slave mode) (see Figure 29 and Figure 30)
t_STE,LEAD
PARAMETER
STE lead time,
STE low to clock
TEST CONDITIONS
V_CC
2.2 V/3 V
MIN TYP
50
t_STE,LAG
STE lag time,
Last clock to STE high
2.2 V/3 V
10
t_STE,ACC
STE access time,
STE low to SOMI data out
2.2 V/3 V
50
t_STE,DIS
STE disable time,
STE high to SOMI high impedance
2.2 V/3 V
50
t_SU,SI
SIMO input data setup time
2.2 V
20
3V
15
t_HD,SI
SIMO input data hold time
2.2 V
10
3V
10
UCLK edge to SOMI valid;
2.2 V
75
t_VALID,SO
SOMI output data valid time
C_L = 20 pF
3V
50
NOTE 1:
f_UCxCLK
=
1
2t_LO∕HI
with
t_LO∕HI
≥
max(t_{VALID,MO(Master)}
+
t_SU,SI(USCI),
t_{SU,MI(Master)}
+
t_{VALID,SO(USCI)})
For the master parameters t_{SU,MI(Master)} and t_{VALID,MO(Master)}, see the SPI parameters of the attached master.
MAX UNIT
ns
ns
ns
ns
ns
ns
110
75 ^ns
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