LM3S608-IQN50-C2 Datasheet, PDF (500/538 Pages) Texas Instruments – Stellaris LM3S608 Microcontroller

Electrical Characteristics
NRND: Not recommended for new designs.
Table 18-10. JTAG Characteristics (continued)
Parameter
No.
Parameter Parameter Name
Min
Nom
J3
t_{TCK_LOW}
TCK clock Low time
J4
t_{TCK_HIGH}
TCK clock High time
J5
t_{TCK_R}
TCK rise time
J6
t_{TCK_F}
TCK fall time
J7
t_{TMS_SU}
TMS setup time to TCK rise
J8
t_{TMS_HLD}
TMS hold time from TCK rise
J9
t_{TDI_SU}
TDI setup time to TCK rise
J10
t_{TDI_HLD}
TDI hold time from TCK rise
2-mA drive
-
t_TCK/2
-
t_TCK/2
0
-
0
-
20
-
20
-
25
-
25
-
23
J11
TCK fall to Data
t _{TDO_ZDV} ^{Valid from High-Z}
4-mA drive
8-mA drive
15
-
14
8-mA drive with slew rate control
18
2-mA drive
21
J12
t _{TDO_DV}
TCK fall to Data
Valid from Data
Valid
4-mA drive
8-mA drive
14
-
13
8-mA drive with slew rate control
18
2-mA drive
9
J13
TCK fall to High-Z
t _{TDO_DVZ} ^{from Data Valid}
4-mA drive
8-mA drive
7
-
6
8-mA drive with slew rate control
7
J14
t_TRST
TRST assertion time
J15
t_{TRST_SU}
TRST setup time to TCK rise
100
-
10
-
Max
-
-
10
10
-
-
-
-
35
26
25
29
35
25
24
28
11
9
8
9
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 18-2. JTAG Test Clock Input Timing
J2
J3
J4
TCK
J6
J5
500
June 18, 2012
Texas Instruments-Production Data