LM3S608-IQN50-C2 Datasheet, PDF (141/538 Pages) Texas Instruments – Stellaris LM3S608 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S608 Microcontroller
4.1
Block Diagram
Figure 4-1. JTAG Module Block Diagram
TRST
TCK
TMS
TDI
TAP Controller
Instruction Register (IR)
BYPASS Data Register
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
TDO
Cortex-M3
Debug
Port
4.2 Signal Description
Table 4-1 on page 141 lists the external signals of the JTAG/SWD controller and describes the
function of each. The JTAG/SWD controller signals are alternate functions for some GPIO signals,
however note that the reset state of the pins is for the JTAG/SWD function. The column in the table
below titled "Pin Assignment" lists the GPIO pin placement for the JTAG/SWD controller signals.
The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 242) is set to
choose the JTAG/SWD function. For more information on configuring GPIOs, see “General-Purpose
Input/Outputs (GPIOs)” on page 224.
Table 4-1. JTAG_SWD_SWO Signals (48QFP)
Pin Name
Pin Number Pin Type Buffer Type^a Description
SWCLK
40
I
TTL
JTAG/SWD CLK.
SWDIO
39
I/O
TTL
JTAG TMS and SWDIO.
SWO
37
O
TTL
JTAG TDO and SWO.
TCK
40
I
TTL
JTAG/SWD CLK.
TDI
38
I
TTL
JTAG TDI.
TDO
37
O
TTL
JTAG TDO and SWO.
TMS
39
I/O
TTL
JTAG TMS and SWDIO.
TRST
41
I
TTL
JTAG TRST.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
June 18, 2012
141
Texas Instruments-Production Data