LM3S608-IQN50-C2 Datasheet, PDF (267/538 Pages) Texas Instruments – Stellaris LM3S608 Microcontroller

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Stellaris^® LM3S608 Microcontroller
8.3.2.1
8.3.2.2
In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access
to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:
GPTMTBILR[15:0]:GPTMTAILR[15:0]
Likewise, a read access to GPTMTAR returns the value:
GPTMTBR[15:0]:GPTMTAR[15:0]
32-Bit One-Shot/Periodic Timer Mode
In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB
registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is
determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register
(see page 277), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register.
When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 281), the
timer begins counting down from its preloaded value. Once the 0x0000.0000 state is reached, the
timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to
be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If
configured as a periodic timer, it continues counting.
In addition to reloading the count value, the GPTM generates interrupts and triggers when it reaches
the 0x000.0000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status
(GPTMRIS) register (see page 286), and holds it until it is cleared by writing the GPTM Interrupt
Clear (GPTMICR) register (see page 288). If the time-out interrupt is enabled in the GPTM Interrupt
Mask (GPTMIMR) register (see page 284), the GPTM also sets the TATOMIS bit in the GPTM Masked
Interrupt Status (GPTMMIS) register (see page 287). The ADC trigger is enabled by setting the
TAOTE bit in GPTMCTL.
If software reloads the GPTMTAILR register while the counter is running, the counter loads the new
value on the next clock cycle and continues counting from the new value.
If the TASTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor
is halted by the debugger. The timer resumes counting when the processor resumes execution.
32-Bit Real-Time Clock Timer Mode
In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers
are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is
loaded with a value of 0x0000.0001. All subsequent load values must be written to the GPTM TimerA
Match (GPTMTAMATCHR) register (see page 292) by the controller.
The input clock on an even CCP input is required to be 32.768 KHz in RTC mode. The clock signal
is then divided down to a 1 Hz rate and is passed along to the input of the 32-bit counter.
When software writes the TAEN bit inthe GPTMCTL register, the counter starts counting up from its
preloaded value of 0x0000.0001. When the current count value matches the preloaded value in the
GPTMTAMATCHR register, it rolls over to a value of 0x0000.0000 and continues counting until
either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs,
the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTMIMR, the
GPTM also sets the RTCMIS bit in GPTMMIS and generates a controller interrupt. The status flags
are cleared by writing the RTCCINT bit in GPTMICR.
If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if
the RTCEN bit is set in GPTMCTL.
June 18, 2012
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