LM3S608-IQN50-C2 Datasheet, PDF (21/538 Pages) Texas Instruments – Stellaris LM3S608 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S608 Microcontroller
Table 1. Revision History (continued)
Date
April 2010
Revision
7004
Description
■ Added caution note to the I²C Master Timer Period (I2CMTPR) register description and changed
field width to 7 bits.
■ Added note about RST signal routing.
■ Clarified the function of the TnSTALL bit in the GPTMCTL register.
■ Additional minor data sheet clarifications and corrections.
January 2010
6712
■ In "System Control" section, clarified Debug Access Port operation after Sleep modes.
■ Clarified wording on Flash memory access errors.
■ Added section on Flash interrupts.
■ Changed the reset value of the ADC Sample Sequence Result FIFO n (ADCSSFIFOn) registers
to be indeterminate.
■ Clarified operation of SSI transmit FIFO.
■ Made these changes to the Operating Characteristics chapter:
– Added storage temperature ratings to "Temperature Characteristics" table
– Added "ESD Absolute Maximum Ratings" table
■ Made these changes to the Electrical Characteristics chapter:
– In "Flash Memory Characteristics" table, corrected Mass erase time
– Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table)
– In "Reset Characteristics" table, corrected supply voltage (VDD) rise time
October 2009
6438
■ The reset value for the DID1 register may change, depending on the package.
■ Deleted MAXADCSPD bit field from DCGC0 register as it is not applicable in Deep-Sleep mode.
■ Deleted reset value for 16-bit mode from GPTMTAILR, GPTMTAMATCHR, and GPTMTAR registers
because the module resets in 32-bit mode.
■ Made these changes to the Electrical Characteristics chapter:
– Removed VSIH and VSIL parameters from Operating Conditions table.
– Changed SSI set up and hold times to be expressed in system clocks, not ns.
– Revised ADC electrical specifications to clarify, including reorganizing and adding new data.
■ Added 48QFN package.
■ Additional minor data sheet clarifications and corrections.
July 2009
5953
■ Clarified Power-on reset and RST pin operation; added new diagrams.
■ Added DBG bits missing from FMPRE register. This changes register reset value.
■ In ADC characteristics table, changed Max value for GAIN parameter from ±1 to ±3 and added E_IR
(Internal voltage reference error) parameter.
■ Corrected ordering numbers.
■ Additional minor data sheet clarifications and corrections.
June 18, 2012
21
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