THS1207 Datasheet, PDF (5/33 Pages) Texas Instruments – 12 bit 4 ANALOG INPUT 6 MSPS SIMULTANEOUS SAMPLING

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THS1207
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
Terminal Functions
TERMINAL
NAME
NO.
AINP
32
I/O
DESCRIPTION
I Analog input, single-ended or positive input of differential channel A
AINM
31
I Analog input, single-ended or negative input of differential channel A
BINP
30
I Analog input, single-ended or positive input of differential channel B
BINM
29
I Analog input, single-ended or negative input of differential channel B
AVDD
AGND
23
I Analog supply voltage
24
I Analog ground
BVDD
BGND
7
I Digital supply voltage for buffer
8
I Digital ground for buffer
CONV_CLK 15
I Digital input. This input is the conversion clock input.
CS0
22
I Chip select input (active low)
CS1
21
I Chip select input (active high)
DGND
17
I Digital ground. Ground reference for digital circuitry.
DVDD
D0 – D9
18
1–6,
9–12
I Digital supply voltage
I/O/Z Digital input, output; D0 = LSB
D10/RA0
13 I/O/Z Digital input, output. The data line D10 is also used as an address line (RA0) for the control register. This is
required for writing to the control register 0 and control register 1. See Table 7.
D11/RA1
14 I/O/Z Digital input, output (D11 = MSB). The data line D11 is also used as an address line (RA1) for the control register.
This is required for writing to control register 0 and control register 1. See Table 7.
REFIN
28
I Common-modereference input for the analog input channels. It is recommended that this pin be connected to the
reference output REFOUT.
REFP
26
I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference voltage.
An external reference voltage at this input can be applied. This option can be programmed through control
register 0. See Table 8.
REFM
25
I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference voltage.
An external reference voltage at this input can be applied. This option can be programmed through control
register 0. See Table 8.
REFOUT
RD(1)
27
O Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 µA. The reference output
requires a capacitor of 10 µF to AGND for filtering and stability.
19
I The RD input is used only if the WR input is configured as a write only input. In this case, it is a digital input, active
low as a data read select from the processor. See timing section.
SYNC
16
O Synchronization output. This signal indicates in a multichannel operation that data of channel A is brought to the
digital output and can therefore be used for synchronization.
WR (R/W)(1) 20
I This input is programmable. It functions as a read-write input R/W and can also be configured as a write-only
input WR, which is active low and used as data write select from the processor. In this case, the RD input is used
as a read input from the processor. See timing section.
(1) _{The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC.}
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