THS1207 Datasheet, PDF (23/33 Pages) Texas Instruments – 12 bit 4 ANALOG INPUT 6 MSPS SIMULTANEOUS SAMPLING

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THS1207
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
Read Timing (using RD, RD-controlled)
Figure 32 shows the read-timing behavior when the WR(R/W) input is programmed as a write-input only. The input
RD acts as the read-input in this configuration. This timing is called RD-controlled because RD is the last external
signal of CS0, CS1, and RD which becomes valid.
CS0
CS1
WR ÓÓÓÓÓÓÓÓ
RD
D(0–9)
DATA_AV
tsu(CS)
10%
tw(RD)
ta
90%
td(CSDAV)
90%
th(CS)
ÔÔÔÔÔÔ
10%
th
90%
Figure 32. Read Timing Diagram Using RD (RD-controlled)
Read Timing Parameter (RD-controlled)
PARAMETER
tsu(CS)
ta
td(CSDAV)
th
th(CS)
tw(RD)
Setup time, RD low to last CS valid
Access time, last CS valid to data valid
Delay time, last CS valid to DATA_AV inactive
Hold time, first CS invalid to data invalid
Hold time, RD change to first CS invalid
Pulse duration, RD active
MIN TYP MAX UNIT
0
ns
0
10 ns
12
ns
0
5 ns
5
ns
10
ns
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