THS1207 Datasheet, PDF (26/33 Pages) Texas Instruments – 12 bit 4 ANALOG INPUT 6 MSPS SIMULTANEOUS SAMPLING

THS1207
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
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Write Timing Diagram (using R/W, CS0-controlled)
Figure 35 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write
input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled
because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid. The writing to the THS1207
can be performed irrespective of the conversion clock signal CONV_CLK.
tw(CS)
CS0
10%
10%
90%
CS1
ÔÔÔ _R/W
ÔÔÔ ^10%
tsu(R/W)
th(R/W)
ÓÓÓÓÓÓ _10%
RD
D(0–11)
tsu
90%
th
90%
Figure 35. Write Timing Diagram Using R/W (CS0-controlled)
Write Timing Parameter (CS0-controlled)
PARAMETER
tsu(R/W)
tsu
th
th(R/W)
tw(CS)
Setup time, R/W stable to last CS valid
Setup time, data valid to first CS invalid
Hold time, first CS invalid to data invalid
Hold time, first CS invalid to R/W change
Pulse duration, CS active
MIN TYP MAX UNIT
0
ns
5
ns
2
ns
5
ns
10
ns
26