THS1207 Datasheet, PDF (16/33 Pages) Texas Instruments – 12 bit 4 ANALOG INPUT 6 MSPS SIMULTANEOUS SAMPLING

THS1207
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
www.ti.com
Figure 28 shows the conversion timing when 3 analog input channels are selected. The maximum throughput
rate per channel is 2 MSPS in this mode. The data flow in the bottom of the figure shows in which order the
converted data is available to the databus. The signal SYNC is always active low if data of channel one is
available to the databus. The data of channel one is followed by the data of channel two and data of channel
three before channel one is again available to the data bus and SYNC is active low.
Sample N
Channel 1, 2, 3
AIN
td(A)
td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
CONV_CLK
tc
tsu(CONV_CLKL-READL)
Sample N+1
Channel 1, 2, 3
tsu(READH-CONV_CLKL)
READ^†
td(CONV_CLKL-SYNCL)
SYNC
Sample N+2
Channel 1, 2, 3
td(CONV_CLKL-SYNCH)
Data N–2
Channel 3
Data N–1
Channel 1
Data N–1
Channel 2
†_{READ is the logical combination from CS0, CS1 and RD}
Data N–1
Channel 3
Data N
Channel 1
Data N
Channel 2
Data N
Channel 3
Figure 28. Conversion Timing in 3-Channel Operation
Figure 29 shows the timing of the conversion mode where 4 analog input channels are selected. The maximum
throughput rate per channel is 1.5 MSPS in this mode. The data flow in the bottom of the figure shows in which
order the converted data is available to the databus. The signal SYNC is active low when data of channel one
is available to the databus. The data of channel one is followed by the data of channel two, data of channel three
and data of channel 4 before channel one is again available to the data bus and SYNC is active low.
Sample N
Channel 1, 2, 3, 4
Sample N+1
Channel 1, 2, 3, 4
AIN
CONV_CLK
READ^†
td(A)
td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
tc
tsu(CONV_CLKL-READL)
tsu(READH-CONV_CLKL)
SYNC
tsu(CONV_CLKL-SYNCL)
tsu(CONV_CLKL-SYNCH)
Data N–1
Channel 1
Data N–1
Channel 2
Data N–1
Channel 3
Data N–1
Channel 4
Data N
Channel 1
Data N
Channel 2
Data N
Channel 3
†_{READ is the logical combination from CS0, CS1 and RD}
Figure 29. Timing of Continuous Conversion Mode (4-channel operation)
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