THS1207 Datasheet, PDF (14/33 Pages) Texas Instruments – 12 bit 4 ANALOG INPUT 6 MSPS SIMULTANEOUS SAMPLING

THS1207
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
www.ti.com
DETAILED DESCRIPTION
Reference Voltage
The THS1207 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V
and VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP
and REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish
the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively.
Analog Inputs
The THS1207 consists of 4 analog inputs, which are sampled simultaneously. These inputs can be selected
individually and configured as single-ended or differential inputs. The desired analog input channel can be
programmed.
Converter
The THS1207 uses a 12-bit pipelined multistaged architecture, which achieves a high sample rate with low
power consumption. The THS1207 distributes the conversion over several smaller ADC sub-blocks, refining
the conversion with progressively higher accuracy as the device passes the results from stage to stage. This
distributed conversion requires a small fraction of the number of comparators used in a traditional flash ADC.
A sample-and-hold amplifier (SHA) within each of the stages permits the first stage to operate on a new input
sample while the second through the eighth stages operate on the seven preceding samples.
Conversion Clock
An external clock signal with a duty cycle of 50% has to be applied to the clock input (CONV_CLK). A new
conversion is started with every falling edge of the applied clock signal. The conversion values are available
at the output with a latency of 5 clock cycles.
SYNC
In multichannel mode, the first SYNC signal is delayed by [7+ (# Channels Sampled)] cycles of the CONV_CLK
after a SYNC reset. This is due to the latency of the pipeline architecture of the THS1207.
Sampling Rate
The maximum possible conversion rate per channel is dependent on the selected analog input channels.
Table 1 shows the maximum conversion rate in the continuous conversion mode for different combinations.
Table 1. Maximum Conversion Rate
CHANNEL CONFIGURATION
1 single-ended channel
2 single-ended channels
3 single-ended channels
4 single-ended channels
1 differential channel
2 differential channels
1 single-ended and 1 differential channel
2 single-ended and 1 differential channels
NUMBER OF
CHANNELS
1
2
3
4
1
2
2
3
MAXIMUM CONVERSION
RATE PER CHANNEL
6 MSPS
3 MSPS
2 MSPS
1.5 MSPS
6 MSPS
3 MSPS
3 MSPS
2 MSPS
The maximum conversion rate in the continuous conversion mode per channel, fc, is given by:
fc
+
6 MSPS
# channels
Conversion
During conversion the ADC operates with a free running external clock applied to the input CONV_CLK. With
every falling edge of the CONV_CLK signal a new converted value is available to the databus with the
corresponding read signal. The THS1207 allows up to four analog input to be selected. The inputs can be
configured as two differential channels, four single-ended channels or a combination of differential and
single-ended.
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