DS92LV2421 Datasheet, PDF (5/50 Pages) National Semiconductor (TI) – 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer

DS92LV2421, DS92LV2422
www.ti.com
SNLS321B – MAY 2010 – REVISED APRIL 2013
DS92LV2421 Serializer Pin Descriptions (continued)
Pin Name
Pin #
I/O, Type Description⁽¹⁾
BISTEN
31
I, LVCMOS BIST Mode — Optional
w/ pull- BISTEN = 0, BIST is disabled (normal operation)
down BISTEN = 1, BIST is enabled
RES[2:0]
18, 16, 15
I, LVCMOS Reserved - tie LOW
w/ pull-
down
Channel-Link II — CML Serial Interface
DOUT+
20
O, CML Non–Inverting Output.
The output must be AC Coupled with a 0.1 µF capacitor.
DOUT-
19
Power and Ground⁽²⁾
O, CML Inverting Output.
The output must be AC Coupled with a 0.1 µF capacitor.
VDDL
7
Power Logic Power, 1.8 V ±5%
VDDP
14
Power PLL Power, 1.8 V ±5%
VDDHS
17
Power TX High Speed Logic Power, 1.8 V ±5%
VDDTX
22
Power Output Driver Power, 1.8 V ±5%
VDDIO
30
Power LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10%
GND
DAP
Ground DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connect to the ground plane (GND) with at least 9 vias.
(2) The VDD (V_DDn and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on
the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
DS92LV2422 Pin Diagram
NC 46
RES 47
VDDIR 48
RIN+ 49
RIN- 50
CMF 51
ROUT+ 52
ROUT- 53
VDDCMLO 54
VDDR 55
ID[x] 56
VDDPR 57
VDDSC 58
PDB 59
NC 60
DS92LV2422
TOP VIEW
DAP = GND
BOLD PIN NAME ± indicates I/O strap
pin associated with output pin
30 NC
29 VDDL
28 DO8/OSC_SEL0
27 DO9/OSC_SEL1
26 DO10/OSC_SEL2
25 DO11
24 VDDIO
23 DO12/EQ0
22 DO13/EQ1
21 DO14/EQ2
20 DO15/EQ3
19 DO16
18 DO17/RFB
17 DO18/OSS_SEL
16 NC
Figure 2. Top View 60-pin WQFN
See Package Number NKB0060B
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