DS92LV2421 Datasheet, PDF (22/50 Pages) National Semiconductor (TI) – 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer

DS92LV2421, DS92LV2422
SNLS321B – MAY 2010 – REVISED APRIL 2013
FUNCTIONAL DESCRIPTION
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The DS92LV2421 / DS92LV2422 chipset transmits and receives 24-bits of data and 3 control signals over a
single serial CML pair operating at 280 Mbps to 2.1 Gbps. The serial stream also contains an embedded clock,
video control signals and the DC-balance information which enhances signal quality and supports AC coupling.
The Des can attain lock to a data stream without the use of a separate reference clock source, which greatly
simplifies system complexity and overall cost. The Des also synchronizes to the Ser regardless of the data
pattern, delivering true automatic “plug and lock” performance. It can lock to the incoming serial stream without
the need of special training patterns or sync characters. The Des recovers the clock and data by extracting the
embedded clock information, validating and then deserializing the incoming data stream providing a parallel
LVCMOS video bus to the display or ASIC/FPGA.
The DS92LV2421 / DS92LV2422 chipset can operate in 24-bit color depth (with DE, HS, VS encoded within the
serial data stream). In 18–bit color applications, the three video control signals maybe sent encoded within the
serial bit stream (restrictions apply) along with six additional general purpose signals.
Block Diagrams for the chipset are shown at the beginning of this datasheet.
Data Transfer
The DS92LV2421 / DS92LV2422 chipset will transmit and receive a pixel of data in the following format: C1 and
C0 represent the embedded clock in the serial stream. C1 is always HIGH and C0 is always LOW. The
remaining 26 bit spaces contain the scrambled, encoded and DC-Balanced serial data.
SER & DES OPERATING MODES AND REVERSE COMPATIBILITY (CONFIG[1:0])
The DS92LV2421 / DS92LV2422 chipset is compatible with other single serial lane Channel Link II or FPD-Link II
devices. Configuration modes are provided for reverse compatibility with the DS90C241 / DS90C124 and also
the DS90UR241 / DS90UR124 by setting the respective mode with the CONFIG[1:0] pins on the Ser or Des as
shown in Table and Table. This selection also determines whether the Control Signal Filter feature is enabled or
disabled in the Normal mode. These configuration modes are selectable the control pins only.
Table 1. DS92LV2421 Ser Modes
CONFIG1 CONFIG0 MODE
L
L
Normal Mode, Control Signal Filter disabled
L
H
Normal Mode, Control Signal Filter enabled
H
L
Reverse Compatibility Mode
H
H
Reverse Compatibility Mode
DES DEVICE
DS92LV2422, DS92LV2412,
DS92LV0422, DS92LV0412
DS92LV2422, DS92LV2412,
DS92LV0422, DS92LV0412
DS90UR124, DS99R124
DS90C124
Table 2. DS92LV2422 Des Modes
CONFIG1 CONFIG0 MODE
L
L
Normal Mode, Control Signal Filter disabled
L
H
Normal Mode, Control Signal Filter enabled
H
L
Reverse Compatibility Mode
H
H
Reverse Compatibility Mode
SER DEVICE
DS92LV2421, DS92LV2411,
DS92LV0421, DS92LV0411
DS92LV2421, DS92LV2411,
DS92LV0421, DS92LV0411
DS90UR241, DS99R421
DS90C241
VIDEO CONTROL SIGNAL FILTER — SER & DES
When operating the devices in Normal Mode, the Control Signals have the following restrictions:
• Normal Mode with Control Signal Filter Enabled: Control Signal 1 and Control Signal 2 — Only 2 transitions
per 130 clock cycles are transmitted, the transition pulse must be 3 parallel clocks or longer.
• Normal Mode with Control Signal Filter Disabled: Control Signal 1 and Control Signal 2 — Only 2 transitions
per 130 clock cycles are transmitted, no restriction on minimum transition pulse.
• Control Signal 3 — Only 1 transition per 130 clock cycles is transmitted , minimum pulse width is 130 clock
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