English
Language : 

DS92LV2421 Datasheet, PDF (33/50 Pages) National Semiconductor (TI) – 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer
DS92LV2421, DS92LV2422
www.ti.com
SNLS321B – MAY 2010 – REVISED APRIL 2013
BER Calculations
It is possible to calculate the approximate Bit Error Rate (BER). The following is required:
• Clock Frequency (MHz)
• BIST Duration (seconds)
• BIST test Result (PASS)
The BER is less than or equal to one over the product of 24 times the CLK rate times the test duration. If we
assume a 65 MHz clock, a 10 minute (600 second) test, and a PASS, the BERT is ≤ 1.07 X 10E-12
The BIST mode runs a check on the data payload bits. The LOCK pin also provides a link status. It the recovery
of the C0 and C1 bits does not reconstruct the expected clock signal, the LOCK pin will switch Low. The
combination of the LOCK and At-Speed BIST PASS pin provides a powerful tool for system evaluation and
performance monitoring.
BISTEN
(SER)
BISTEN
(DES)
CLKOUT
(RFB = L)
DO[23:0]
CO1,CO2,CO3
DATA
(internal)
PASS
Prior Result
DATA
X
(internal)
PASS
Prior Result
Normal
PRBS
X = bit error(s)
X
X
BIST Test
BIST Duration
PASS
FAIL
BIST
Result
Held
Normal
Figure 29. BIST Waveforms
Optional Serial Bus Control
The Ser and Des may also be configured by the use of a serial control bus that is I2C protocol compatible. By
default, the I2C reg_0x00'h is set to 00'h and all configuration is set by control/strap pins. A write of 01'h to
reg_0x00'h will enable/allow configuration by registers; this will override the control/strap pins. Multiple devices
may share the serial control bus since multiple addresses are supported. See Figure 30.
The serial bus is comprised of three pins. The SCL is a Serial Bus Clock Input. The SDA is the Serial Bus Data
Input / Output signal. Both SCL and SDA signals require an external pull up resistor to VDDIO. For most
applications a 4.7 k pull up resistor to VDDIO may be used. The resistor value may be adjusted for capacitive
loading and data rate requirements. The signals are either pulled High, or driven Low.
Copyright © 2010–2013, Texas Instruments Incorporated
Submit Documentation Feedback
33
Product Folder Links: DS92LV2421 DS92LV2422