DS92LV2421 Datasheet, PDF (40/50 Pages) National Semiconductor (TI) – 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer

DS92LV2421, DS92LV2422
SNLS321B – MAY 2010 – REVISED APRIL 2013
www.ti.com
1.8V
C13 C11
C3
C4
C5
C15 C6
DS92LV2422 (DES)
VDDL
VDDIO
C8
VDDSC
VDDIO
C9
VDDPR
VDDIO
C10
VDDR
VDDIR
VDDIO
C12 C14
C16 C7
VDDCMLO
VDDIO
Serial
Channel Link II
Interface
C1
C2
C17
RIN+
RIN-
CMF
Host
Control
TP_A
TP_B
C18
1.8V
10k
RID
C1 - C2 = 0.1 PF (50 WV)
C3 - C12 = 0.1 PF
C13, C16 = 4.7 PF
C17, C18 = >10 PF
RID (see ID[x] Resistor Value Table 13)
FB1-FB4: Impedance = 1 k:,
low DC resistance (<1:)
ROUT+
ROUT-
BISTEN
PDB
ID[X]
SCL
SDA
NC
8
RES
DAP (GND)
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
DO9
DO10
DO11
DO12
DO13
DO14
DO15
DO16
DO17
DO18
DO19
DO20
DO21
DO22
DO23
CO1
CO2
CO3
CLKOUT
LOCK
PASS
EXAMPLE:
STRAP
Input
Pull-Ups
(10k)
LVCMOS
Parallel
Video
Interface
Figure 35. DS92LV2422 Typical Connection Diagram — Pin Control
POWER UP REQUIREMENTS AND PDB PIN
The VDD (V_DDn and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms
then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the
recommended operating voltage. When PDB pin is pulled to V_DDIO, it is recommended to use a 10 kΩ pull-up and
a 22 uF cap to GND to delay the PDB input signal.
40
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS92LV2421 DS92LV2422