DS92LV2421 Datasheet, PDF (14/50 Pages) National Semiconductor (TI) – 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer

DS92LV2421, DS92LV2422
SNLS321B – MAY 2010 – REVISED APRIL 2013
Serializer Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
λ_STXBW Serializer Jitter Transfer
Function -3 dB Bandwidth
R_L = 100Ω, De-Emph = disabled,
RANDOM pattern, CLKIN = 75MHz
R_L = 100Ω, De-Emph = disabled,
RANDOM pattern, CLKIN = 43MHz
R_L = 100Ω, De-Emph = disabled,
RANDOM pattern, CLKIN = 10MHz
δ_STX
Serializer Jitter Transfer
Function Peaking
R_L = 100Ω, De-Emph = disabled,
RANDOM pattern, CLKIN = 75MHz
R_L = 100Ω, De-Emph = disabled,
RANDOM pattern, CLKIN = 43MHz
R_L = 100Ω, De-Emph = disabled,
RANDOM pattern, CLKIN = 10MHz
Min ⁽¹⁾
www.ti.com
Typ Max⁽¹⁾ Units
3.3
MHz
2.3
MHz
0.8
MHz
0.86
dB
0.83
dB
0.28
dB
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
t_RCP
CLK Output Period
t_RDC
CLK Output Duty Cycle
t_RCP = t_TCP
SSCG = OFF,
10 – 75 MHz
CLKOUT
SSCG = ON,
10 – 20MHz
SSCG = ON,
10 – 65MHz
t_CLH
LVCMOS
Low-to-High
Transition Time, Figure 12
V_DDIO = 1.8V,
C_L = 4pF,
OS_CLKOUT/DATA = L
CLKOUT
V_DDIO = 3.3V
C_L = 4pF,
OS_CLKOUT/DATA = H
t_CHL
LVCMOS
High-to-Low
Transition Time, Figure 12
V_DDIO = 1.8V,
C_L = 4pF,
OS_CLKOUT/DATA = L
CLKOUT
V_DDIO = 3.3V
C_L = 4pF,
OS_CLKOUT/DATA = H
t_ROS
t_ROH
t_DDLT
Data Valid before CLKOUT –
Set Up Time, Figure 16
V_DDIO = 1.71 to 1.89V or 3.0 DO[23:0], CO1, CO2,
to 3.6V
CO3
C_L = 4pF (lumped load)
Data Valid after CLKOUT – Hold V_DDIO = 1.71 to 1.89V or 3.0 DO[23:0], CO1, CO2,
Time, Figure 16
to 3.6V
CO3
C_L = 4pF (lumped load)
Deserializer Lock Time,
SSC[3:0] = OFF⁽³⁾
CLKOUT = 10MHz
Figure 15
SSC[3:0] = OFF⁽³⁾
CLKOUT = 75MHz
SSC[3:0] = ON⁽³⁾
CLKOUT = 10MHz
SSC[3:0] = ON⁽³⁾
CLKOUT = 65MHz
t_DD
Des Delay - Latency, Figure 13
t_DPJ
Des Period Jitter
SSC[3:0] = OFF⁽⁴⁾
CLKOUT = 10 to 75 MHz
CLKOUT = 10 MHz
CLKOUT = 65 MHz
CLKOUT = 75 MHz
Min ⁽¹⁾
13.3
40
35
40
0.23
0.33
Typ Max⁽¹⁾ Units
T
100
ns
50
60
%
59
65
%
53
60
%
2.1
ns
2.0
ns
1.6
ns
1.5
ns
0.5
UI ⁽²⁾
0.5
UI ⁽²⁾
3
ms
4
ms
30
ms
6
ms
139*T 140*T ns
500 1000 ps
550 1250 ps
435
900
ps
(1) Specification is verified by design and is not tested in production.
(2) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 28*CLK). The UI scales with clock frequency.
(3) t_PLD and t_DDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active clock.
(4) t_DPJ is the maximum amount the period is allowed to deviate over many samples.
14
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS92LV2421 DS92LV2422