DS92LV2421 Datasheet, PDF (23/50 Pages) National Semiconductor (TI) – 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer

DS92LV2421, DS92LV2422
www.ti.com
SNLS321B – MAY 2010 – REVISED APRIL 2013
cycles.
Control Signals are defined as low frequency signals with limited transition. Glitches of a control signal can cause
a visual error in display applications. This feature allows for the chipset to validate and filter out any high
frequency noise on the control signals. See Figure.
SERIALIZER Functional Description
The Ser converts a wide parallel input bus to a single serial output data stream, and also acts as a signal
generator for the chipset Built In Self Test (BIST) mode. The device can be configured via external pins or
through the optional serial control bus. The Ser features enhance signal quality on the link by supporting: a
selectable VOD level, a selectable de-emphasis signal conditioning and also the Channel Link II data coding that
provides randomization, scrambling, and DC Balanacing of the data. The Ser includes multiple features to reduce
EMI associated with display data transmission. This includes the randomization and scrambling of the data and
also the system spread spectrum clock support. The Ser features power saving features with a sleep mode, auto
stop clock feature, and optional LVCMOS (1.8 V) parallel bus compatibility.
See also the Functional Description of the chipset's serial control bus and BIST modes.
EMI Reduction Features
Data Randomization & Scrambling
Channel Link II Ser / Des feature a 3 step encoding process which enables the use of AC coupled interconnects
and also helps to manage EMI. The serializer first passes the parallel data through a scrambler which
randomizes the data. The randomized data is then DC balanced. The DC balanced and randomized data then
goes through a bit shuffling circuit and is transmitted out on the serial line. This encoding process helps to
prevent static data patterns on the serial stream. The resulting frequency content of the serial stream ranges
from the parallel clock frequency to the nyquist rate. For example, if the Ser / Des chip set is operating at a
parallel clock frequency of 75 MHz, the resulting frequency content of serial stream ranges from 75 MHz to 1.05
GHz ( 75 MHz *28 bits = 2.1 Gbps / 2 = 1.05 GHz ).
Ser — Spread Spectrum Compatibility
The Ser CLKIN is capable of tracking spread spectrum clocking (SSC) from a host source. The CLKIN will
accept spread spectrum tracking up to 35 kHz modulation and ±0.5, ±1 or ±2% deviations (center spread). The
maximum conditions for the CLKIN input are: a modulation frequency of 35 kHz and amplitude deviations of ±2%
(4% total).
Integrated Signal Conditioning Features — Ser
Ser — VOD Select (VODSEL)
The Ser differential output voltage may be increased by setting the VODSEL pin High. When VODSEL is Low,
the VOD is at the standard (default) level. When VODSEL is High, the VOD is increased in level. The increased
VOD is useful in extremely high noise environments and also on extra long cable length applications. When
using de-emphasis it is recommended to set VODSEL = H to avoid excessive signal attenuation especially with
the larger de-emphasis settings. This feature may be controlled by the external pin or by register.
Table 3. Differential Output Voltage
Input
VODSEL
H
L
VOD
mV
±420
±280
Effect
VOD
mVp-p
840
560
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