DS92LV2421 Datasheet, PDF (26/50 Pages) National Semiconductor (TI) – 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer

DS92LV2421, DS92LV2422
SNLS321B – MAY 2010 – REVISED APRIL 2013
www.ti.com
Des — Common Mode Filter Pin (CMF) — Optional
The Des provides access to the center tap of the internal termination. A capacitor may be placed on this pin for
additional common-mode filtering of the differential pair. This can be useful in high noise environments for
additional noise rejection capability. A 4.7 µF capacitor may be connected to this pin to Ground.
Des — SSCG Generation — Optional
The Des provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both clock and
data outputs are modulated. This will aid to lower system EMI. Output SSCG deviations to ±2% (4% total) at up
to 100 kHz modulations is available. Note: The device supports SSCG function with CLK = 10 MHz to 65 MHz.
When the CLK = 65 MHz to 75 MHz, it is required to disable SSCG function (SSC[3:0] = 0000). See Table 6.
This feature may be controlled by external STRAP pins or by register.
Frequency
F_CLKOUT+
F_CLKOUT
F_CLKOUT-
fdev(max)
1/fmod
Figure 22. SSCG Waveform
fdev(min)
Time
Table 6. SSCG Configuration (LF_MODE = L) — Des Output
SSC3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
SSC[3:0] Inputs
LF_MODE = L (20 - 65 MHz)
SSC2
SSC1
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
SSC0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Result
fdev (%)
NA
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
fmod (kHz)
Disable
CLK/2168
CLK/1300
CLK/868
CLK/650
26
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