CDC5801 Datasheet, PDF (5/16 Pages) Texas Instruments – LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY AND PHASE ALIGNMENT

CDC5801
LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH
PROGRAMMABLE DELAY AND PHASE ALIGNMENT
SCAS682A – OCTOBER 2002
PLL divider/multiplier selection
Table 1 and Table 2 list the supported REFCLK and BUSCLK (CLKOUT/CLKOUTB) frequencies.
Table 1. Multiplication Ratios (P0:2 = 000 or 100)
MULT0
0
0
1
MULT1
0
1
1
REFCLK
(MHZ)
38–125
25–83.3
19–62.5
MULTIPLICATION
RATIO
4
6
8
BUSCLK
(MHZ)
152–500
150–500
152–500
MULT0
0
1
1
Table 2. Divider Ratio (P0:2 = 001)
MULT1
0
0
1
REFCLK
(MHZ)
100–125
75–93
50–62
DIVISION
RATIO
2
3
4
BUSCLK
(MHZ)
50–62.5
25–31
12.5–15.5
STATE
Powerdown
CLK stop
Normal
Table 3. Clock Output Driver States
PWRDNB
0
1
1
STOPB
X
0
1
CLKOUT
GND
VO, _STOP
As per Function Table
CLKOUTB
GND
VO, _STOP
As per Function Table
Table 4. Programmable Delay and Phase Alignment
DLYCTRL
LEADLAG
CLKOUT AND CLKOUTB
Each rising edge^†
1
Will be advanced by one step size (see Table 5)
Each rising edge^†
0
Will be delayed by one step size (see Table 5)
† _{For every 32nd edge, there are one or two edges the phase aligner does not update. Therefore,}
CLKOUT phase is not updated on every 32nd edge.
Table 5. Clock Output Driver States
FUNCTIONALITY
STEP SIZE
Multiply by 4, 6, 8
CLKOUT period/384 (for example, 6.5 ps @ 400 MHz)
Divide by 2
CLKOUT period/3072 (for example, 6.5 ps @ 50 MHz)
Divide by 3
CLKOUT period/6144 (for example, 6.5 ps @ 25 MHz)
Divide by 4
CLKOUT period/12288 (for example, 6.5 ps @ 12.5 MHz)
NOTE: The frequency of the DLYCTRL terminal must always be equal or less than the
frequency of the LEADLAG terminal.
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