CDC5801 Datasheet, PDF (3/16 Pages) Texas Instruments – LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY AND PHASE ALIGNMENT

functional block diagram
CDC5801
LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH
PROGRAMMABLE DELAY AND PHASE ALIGNMENT
SCAS682A – OCTOBER 2002
PWRDWNB P0
P1
P2
Control Logic
STOPB
REFCLK
B
VDDREF/2
PLLCLK
Phase Aligner
Bypass MUX
PLL
Phase
Aligner
Divider
Ratio
φ_D
A
CLKOUT
CLKOUTB
VDDPD/2
2 MULT0/DIV0
MULT1/DIV1
DLYCTRL LEADLAG
FUNCTION TABLE^†
MODE
P0 P1 P2
CLKOUT/CLKOUTB
Multiplication with programmable 0 0 0 REFCLK multiplied by ratio per Table 1 selected by MULT/DIV terminals. Outputs
delay and phase alignment active^‡
are delayed or advanced based on DLYCTRL and LEADLAG terminal
configuration.
Division with programmable delay 0 0 1 REFCLK divided by ratio per Table 2 selected by MULT/DIV terminals. Outputs
and phase alignment active ^‡
are delayed or advanced based on DLYCTRL and LEADLAG terminal
configuration.
Multiplication only mode (phase
aligner bypassed) ^§
1 0 0 In this mode one can only multiply as per Table 1. Programmable delay capability
and divider capability is deactivated. PLL is running.
Test mode
1 1 0 PLL and phase aligner both bypassed. REFCLK is directly channeled to output.
Hi-Z mode
0 1 X Hi-Z
† _{X = don’t care, Hi-Z = high impedance}
‡ _{Please see Table 4 and Table 5 for explanation for the programmability and phase alignment functions.}
§ _{In this mode the DLYCTRL and LEADLAG terminals must be strapped high or low. Lowest possible jitter is achieved in this mode, but a delay}
of 200 ps to 2 ns expected typically from REFCLK to CLKOUT depending on the output frequency.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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