CDC5801 Datasheet, PDF (4/16 Pages) Texas Instruments – LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY AND PHASE ALIGNMENT

CDC5801
LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH
PROGRAMMABLE DELAY AND PHASE ALIGNMENT
SCAS682A – OCTOBER 2002
Terminal Functions
TERMINAL
NAME
NO.
CLKOUT
20
CLKOUTB
18
DLYCTRL
7
GND
GNDO
GNDP
GNDPA
LEADLAG
MULT0/DIV0
MULT1/DIV1
NC
PWRDNB
P0
P1
P2
REFCLK
STOPB
VDDPA
VDDPD
VDDREF
VDDO
VDDP
5
17, 21
4
8
6
15
14
19
12
24
23
13
2
11
9
10
1
16, 22
3
I/O
DESCRIPTION
O Output clock
O Output clock (complement)
I Every rising edge on this terminal delays/advances the CLKOUT/CLKOUTB signal by 1/384th of the
CLKOUT/CLKOUTB period. (e.g., for a 90 degree delay or advancement one needs to provide 96 rising
edges). See Table 4.
GND for VDDREF and VDDPD
GND for clock output terminals (CLKOUT, CLKOUTB)
GND for PLL
GND for phase aligner
I Decides if the output clock is delayed or advanced with respect to REFCLK. See Table 4.
I PLL multiplier and divider select
I PLL multiplier and divider select
Not used
I Active low power down state, CLKOUT/CLKOUTB goes low
I Mode control, see Function Table
I Mode control, see Function Table
I Mode control, see Function Table
I Reference input clock
I Active low output disabler, PLL and PA still running, CLKOUT and CLKOUTB goes to a dc value as per Table 3
I Supply voltage for phase aligner
I Reference voltage for the DLYCTRL, LEADLAG terminals and STOPB function
I Reference voltage for REFCLK
I Supply voltage for the output terminals (CLKOUT, CLKOUTB)
I Supply voltage for PLL
4
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